PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 204

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
13-4
Figure 13-2. Flow chart of system boot procedure for both host-assisted and autonomous configurations.
(Host driver will complete
System boot halts
the boot procedure)
No
2 bits: PNX1300 clock speed
size register in PCI BIU
3 bits: DRAM aperture size
DRAM_ROUND_SIZE
Write aperture size to
Wait ca. 0.6 msec for
clock speed register
registers in PCI BIU
1 bit: Test mode control
to activate highway
1 bit: EPROM capacity
Write to EEPROM
Write to PNX1300
Wait 400 usec for
32-bit serial read
SUBSYSTEM ID
24-bit serial read
8-bit serial read:
1 bit: I
8-bit serial read
8-bit serial read
Write 20 bits to
register in MMI
register in MMI
I
MM_CONFIG
PLL_RATIOS
TRI_RESET#
MMI_RESET
2
Autonomous
size register
PLLs to lock
PRELIMINARY SPECIFICATION
de-asserted
C to stabilize
Write to
Write to
Disable
2
Boot
C clock rate
Yes
Write 32 bits of code onto highway
Then execute 15 dummy writes on
highway to meet MMI protocol.
with all byte enables active.
32-bit serial read
Write to SDRAM
Decrement byte
count by four
DRAM_CACHEABLE_LIMIT
No
64-bit serial read
64-bit serial read
64-bit serial read
32-bit serial read
8-bit serial read
Bytecount == 0
DRAM_BASE
MMIO space:
MMIO_BASE
MMIO space:
MMIO space:
Save 11-bit
byte count
Write to
Write to
Write to
Philips Semiconductors
DRAM_BASE in big-endian mode.
DSPCPU starts execution at
Write to MMIO space:
Disable CPU_RESET.
System boot halts
Yes