PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 511

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

MMIO Register Summary
B.1
The following table lists all the MMIO registers implemented in PNX1300/01/02/11. The registers are grouped accord-
ing to the unit to which they belong. For compatibility with future devices, any undefined MMIO bits should be ignored
when read, and written as zeroes.
DRAM_BASE
DRAM_LIMIT
MMIO_BASE
EXCVEC
ISETTING0
ISETTING1
ISETTING2
ISETTING3
IPENDING
ICLEAR
IMASK
INTVEC0
INTVEC1
INTVEC2
INTVEC3
INTVEC4
INTVEC5
INTVEC6
INTVEC7
INTVEC8
INTVEC9
INTVEC10
INTVEC11
INTVEC12
INTVEC13
INTVEC14
INTVEC15
INTVEC16
INTVEC17
INTVEC18
INTVEC19
MMIO Register Name
MMIO REGISTERS
10 0000
10 0004
10 0400
10 0800
10 0810
10 0814
10 0818
10 0820
10 0824
10 0828
10 0880
10 0884
10 0888
10 0890
10 0894
10 0898
10 08a0
10 08a4
10 08a8
10 08b0
10 08b4
10 08b8
(in hex)
10 081c
10 088c
10 089c
10 08ac
10 08bc
10 08c0
10 08c4
10 08c8
10 08cc
Offset
DSPCPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Accessibility
DSPCPU Registers
Initiators
External
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCI
PRELIMINARY SPECIFICATION
Start of DRAM address aperture
End of DRAM address aperture
Start of 2-MB MMIO-register address aperture
Interrupt vector (handler start address) for exceptions
Interrupt mode & priority settings for sources 0-7
Interrupt mode & priority settings for sources 8-15
Interrupt mode & priority settings for sources 16-23
Interrupt mode & priority settings for sources 24-31
Interrupt-pending status bit for all 32 sources
Interrupt-clear bit for all 32 sources
Interrupt-mask bit for all 32 sources
Interrupt vector (handler start address) for source 0
Interrupt vector (handler start address) for source 1
Interrupt vector (handler start address) for source 2
Interrupt vector (handler start address) for source 3
Interrupt vector (handler start address) for source 4
Interrupt vector (handler start address) for source 5
Interrupt vector (handler start address) for source 6
Interrupt vector (handler start address) for source 7
Interrupt vector (handler start address) for source 8
Interrupt vector (handler start address) for source 9
Interrupt vector (handler start address) for source 10
Interrupt vector (handler start address) for source 11
Interrupt vector (handler start address) for source 12
Interrupt vector (handler start address) for source 13
Interrupt vector (handler start address) for source 14
Interrupt vector (handler start address) for source 15
Interrupt vector (handler start address) for source 16
Interrupt vector (handler start address) for source 17
Interrupt vector (handler start address) for source 18
Interrupt vector (handler start address) for source 19
by Gert Slavenburg, and Selliah Rathnam
Description
Chapter B
B-1