PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 430

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
32-bit load with scaled index
SYNTAX
FUNCTION
DESCRIPTION
result in rdest. If the memory address computed by rsrc1 + 4×rsrc2 is not a multiple of 4, the result of
undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xcfc, r30 = 0x1,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r50 = 0, r40 = 0xd0c, r20 = 0xfffffffe,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r60 = 1, r40 = 0xd0c, r20 = 0xfffffffe,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r70 = 0xd01, r30 = 0x1
The
The
The
[ IF rguard ] ld32x rsrc1 rsrc2 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
rdest<7:0> ← mem[rsrc1 + (4 × rsrc2) +(3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + (4 × rsrc2) + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + (4 × rsrc2) + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + (4 × rsrc2) + (0 ⊕ bs)]
ld32x
ld32x
ld32x
bs ← 3
bs ← 0
Initial Values
ld32x
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation loads the 32-bit memory value from the address computed by rsrc1 + 4×rsrc2 and stores the
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
ld32x r10 r30 → r100
IF r50 ld32x r40 r20 → r80
IF r60 ld32x r40 r20 → r90
ld32x r70 r30 → r110
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r100 ← 0x84332211
no change, since guard is false
r90 ← 0x48665544
r110 undefined, since 0xd01 + 4×1 is not a
multiple of 4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ld32 ld32d ld32r st32
st32d h_st32d
ATTRIBUTES
SEE ALSO
Result
ld32x
ld32x
ld32x
dmem
201
4, 5
No
—
2
3
A-132
.
is