PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 227

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
factory-supplied state machine that resides in SDRAM. It
is read each time the ICP executes an operation. Using
an SDRAM-resident microprogram-controlled state ma-
chine minimizes hardware and provides flexibility in han-
dling special conditions without additional hardware.
Important Note: You must set the ICP DMA Enable bit
(IE) in the BIU_CTL register of the PCI interface for RGB
output to PCI. This bit must be set before initiating RGB
to PCI operations, or the ICP will stall waiting for the PCI
to become ready. Refer to
Register.”
14.6.1
The ICP is controlled by the DSPCPU through five MMIO
registers: the MicroProgram Counter (MPC), the Micro
Instruction Register (MIR), the Data Pointer (DP), the
Data Register (DR) and the ICP Status register (SR), as
shown in
in normal operations, and the MIR and DR are used in
test and debug. Note that the MMIO registers should
never be written while the ICP is executing microcode, i.e
test the Busy bit in the SR register before writing any ICP
MMIO register.
The MPC is the MCU instruction counter. It points to the
next microinstruction to be executed. The entry point in
the microprogram defines which ICP operation is to be
executed.The DP points to the location in SDRAM of a
table of parameters used by the ICP to process the im-
age data, such as the image input and output start ad-
dresses, scaling factor, etc.
The SR has 13 active bits: Busy (B), Done (D), done In-
terrupt Enable (IE), ACK_DONE (A), Little Endian (L),
Step (S), Diagnostic (DG), Reset (R), Priority Delay (PD,
4 bits). Bits 12 .. 30 are reserved.
Figure 14-17. ICP MMIO Registers
MMIO Offsets
0x10 2400
0x10 2404
0x10 2408
0x10 2410
0x10 2414
Figure
ICP Register Model
14-17. The MPC, DP and SR are used
31
31
Section 11.6.5, “BIU_CTL
30
ICP Status (ICP_SR)
MicroProgram Counter (MPC, ICP_MPC)
MicroInstruction Register (MIR, ICP_MIR)
Data Pointer (DP, ICP_DP)
Data Register (DR, ICP_DR)
12 11
Priority Delay
• (B)usy indicates the ICP is busy executing micro-
• (D)one indicates that the previous requested function
• (D)one causes an interrupt to the DSPCPU when
• (A)CK_DONE clears (D)one and the corresponding
• (L)ittle Endian sets the highway endian swap multi-
• (S)tep causes the MCU to execute one microinstruc-
• (DG) allows SDRAM operations in step mode.
• (R) is a write-only bit that resets ICP internal regis-
• (PD) sets a timer for bus activity that defines the min-
The ICP Status Register contains 20 read-only status
bits. The upper 16 bits of the Status Register can contain
a 16-bit code returned by the microprogram upon com-
pletion. Bits 15 through 12 are reserved for error flags.
Important Note: You must set the ICP DMA Enable bit
(IE) in the BIU_CTL register of the PCI interface for RGB
output to PCI. This bit must be set before initiating RGB
to PCI operations, or the ICP will stall waiting for the PCI
to become ready. Refer to
Register.”
14.6.2
The ICP block enters in power down state whenever
PNX1300 is put in global power down mode.
PRELIMINARY SPECIFICATION
code.
is complete, and that the ICP clock is stopped.
Interrupt Enable is set.
interrupt.
plexer to little endian mode for data on the SDRAM
bus.
ters.
imum bus bandwidth available to the ICP.
tion. Step is used for diagnostics to step the ICP
through its microinstructions one clock step at a time.
Writing a ‘1’ to Step sets Busy, which is reset at the
end of execution of the next microinstruction.
8
Power Down
R
7
DG
6
S
5
L
4
Section 11.6.5, “BIU_CTL
Image Coprocessor
A
3
IE
2
0
D
1
0
B
14-17