SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 131

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

SuperI/O Module
5.8.2
Both SP1 and SP2 provide UART functionality. The generic
SP1 and SP2 support serial data communication with
remote peripheral device or modem using a wired inter-
face. The functional blocks can function as a standard
16450, 16550, or as an Extended UART.
5.8.2.1
Four register banks, each containing eight registers, control
UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h. The BSR regis-
ter selects the active bank and is common to all banks. See
Figure 5-18.
5.8.2.2
The tables in this subsection provide register and bit maps
for Banks 0 through 3.
1.
AMD Geode™ SC2200 Processor Data Book
When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38.
Offset
00h
01h
02h
03h
04h
05h
06h
07h
UART Functionality (SP1 and SP2)
UART Mode Register Bank Overview
SP1 and SP2 Register and Bit Maps for UART
Functionality
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
W
W
Name
RXD. Receiver Data Port
TXD. Transmitter Data Port
IER. Interrupt Enable
EIR. Event Identification (Read Cycles)
FCR. FIFO Control (Write Cycles)
LCR
BSR
MCR. Modem/Mode Control
LSR. Link Status
MSR. Modem Status
SPR. Scratchpad
ASCR. Auxiliary Status and Control
Table 5-37. Bank 0 Register Map
1
1
. Line Control
.Bank Select
Offset 07h
Offset 06h
Offset 05h
Offset 04h
Offset 02h
Offset 01h
Offset 00h
LCR/BSR
Figure 5-18. UART Mode Register Bank
Bank 0
Bank 1
Bank 2
Bank 3
Architecture
16550 Banks
32580B
Throughout
All Banks
Common
Register
137