SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 23

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Architecture Overview
2.3
The Core Logic module is described in detail in Section 6.0
"Core Logic Module" on page 149.
The Core Logic module is connected to the Fast-PCI bus. It
uses signal AD28 as the IDSEL for all PCI configuration
functions except for USB which uses AD29.
2.3.1
The following interfaces of the Core Logic module are
implemented via external balls of the SC2200. Each inter-
face is listed below with a reference to the descriptions of
the relevant balls.
• IDE: See Section 3.4.9 "IDE Interface Signals" on page
• AC97: See Section 3.4.14 "AC97 Audio Interface
• PCI: See Section 3.4.6 "PCI Bus Interface Signals" on
• USB: See Section 3.4.10 "Universal Serial Bus (USB)
• LPC: See Section 3.4.8 "Low Pin Count (LPC) Bus Inter-
• Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals"
• GPIO: See Section 3.4.16 "GPIO Interface Signals" on
• More detailed information about each of these interfaces
• Super/IO Block Interfaces: See Section 4.2 "Multi-
AMD Geode™ SC2200 Processor Data Book
63.
Signals" on page 68.
page 57.
Interface Signals" on page 64. The USB function uses
signal AD29 as the IDSEL for PCI configuration.
face Signals" on page 62.
on page 61, Section 6.2.5 "Sub-ISA Bus Interface" on
page 155, and Section 4.2 "Multiplexing, Interrupt Selec-
tion, and Base Address Registers" on page 76
page 70.
is provided in Section 6.2 "Module Architecture" on page
150.
plexing, Interrupt Selection, and Base Address Regis-
ters" on page 76, Section 3.4.5 "ACCESS.bus Interface
Signals" on page 57, Section 3.4.13 "Fast Infrared (IR)
Port Interface Signals" on page 67, and Section 3.4.12
"Parallel Port Interface Signals" on page 66.
Core Logic Module
Other Interfaces of the Core Logic
Module
The Core Logic module interface to the GX1 module con-
sists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• PSERIAL is a one-way serial bus from the GX1 to the
• IRQ13 is an input from the GX1 module indicating that a
• INTR is the level output from the integrated 8259A PICs
• SMI# is a level-sensitive interrupt to the GX1 module
• SUSP# and SUSPA# are handshake signals for imple-
• CPU_RST resets the CPU and is asserted for approxi-
• PCI bus interface signals.
2.4
The SuperI/O (SIO) module is PC98 and ACPI compliant. It
offers a single-cell solution to the most commonly used ISA
peripherals.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
Core Logic module used to communicate power-
management states and VSYNC information for VGA
emulation.
floating point error was detected and that INTR should
be asserted.
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
that can be configured to assert on a number of different
system events. After an SMI# assertion, SMM is entered
and program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
menting CPU Clock Stop and clock throttling.
mately 100 µs after the negation of POR#.
SuperI/O Module
32580B
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