SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 284

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

296
Note:
Offset 10h-13h
Note:
Offset 14h-17h
29:7
29:7
Bit
31
30
31
30
6
5
4
3
2
1
0
6
5
4
3
2
1
0
All bits are set by hardware and cleared by software.
Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Description
RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has
changed.
FrameNumberOverflow. Set when bit 15 of FrameNumber changes value.
UnrecoverableError (Read Only). This event is not implemented and is hard-coded to 0. Writes are ignored.
ResumeDetected. Set when HC detects resume signaling on a downstream port.
StartOfFrame. Set when the Frame Management block signals a Start of Frame event.
WritebackDoneHead. Set after the HC has written HcDoneHead to HccaDoneHead.
SchedulingOverrun. Set when the List Processor determines a Schedule Overrun has occurred.
MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.
OwnershipChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Ownership Change.
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable.
0: Ignore.
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable.
0: Ignore.
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable.
0: Ignore.
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable.
0: Ignore.
1: Enable interrupt generation due to Writeback Done Head.
SchedulingOverrunEnable.
0: Ignore.
1: Enable interrupt generation due to Scheduling Overrun.
MasterInterruptEnable. Global interrupt disable. A write of 1 disables all interrupts.
OwnershipChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Ownership Change.
Reserved. Read/Write 0s.
Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
32580B
HcInterruptDisable Register (R/W)
HcInterruptEnable Register (R/W)
Core Logic Module - USB Controller Registers - PCIUSB
AMD Geode™ SC2200 Processor Data Book
Reset Value = 00000000h
Reset Value = 00000000h