SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 153

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Core Logic Module
DMA Transfer Modes
Each DMA channel can be programmed for single, block,
demand or cascade transfer modes. In the most commonly
used mode, single transfer mode, one DMA cycle occurs
per DRQ and the PCI bus is released after every cycle.
This allows the Core Logic module to timeshare the PCI
bus with the GX1 module. This is imperative, especially in
cases involving large data transfers, because the GX1
module gets locked out for too long.
In block transfer mode, the DMA controller executes all of
its transfers consecutively without releasing the PCI bus.
In demand transfer mode, DMA transfer cycles continue to
occur as long as DRQ is high or terminal count is not
reached. In this mode, the DMA controller continues to exe-
cute transfer cycles until the I/O device drops DRQ to indi-
cate its inability to continue providing data. For this case,
the PCI bus is held by the Core Logic module until a break
in the transfers occurs.
In cascade mode, the channel is connected to another
DMA controller or to an ISA bus master, rather than to an
I/O device. In the Core Logic module, one of the 8237 con-
trollers is designated as the master and the other as the
slave. The HOLD output of the slave is tied to the DRQ0
input of the master (Channel 4), and the master’s DACK0#
output is tied to the slave’s HLDA input.
In each of these modes, the DMA controller can be pro-
grammed for read, write, or verify transfers.
Both DMA controllers are reset at power-on reset (POR) to
fixed priority. Since master Channel 0 is actually connected
to the slave DMA controller, the slave’s four DMA channels
have the highest priority, with Channel 0 as highest and
Channel 3 as the lowest. Immediately following slave
Channel 3, master Channel 1 (Channel 5) is the next high-
est, followed by Channels 6 and 7.
DMA Controller Registers
The DMA controller can be programmed with standard I/O
cycles to the standard register space for DMA. The I/O
addresses for the DMA controller registers are listed Table
6-43 on page 305.
When writing to a channel's address or WORD Count reg-
ister, the data is written into both the base register and the
current register simultaneously. When reading a channel
address or WORD Count register, only the current address
or WORD Count can be read. The base address and base
WORD Count are not accessible for reading.
DMA Transfer Types
Each of the seven DMA channels may be programmed to
perform one of three types of transfers: read, write, or ver-
ify. The transfer type selected defines the method used to
transfer a byte or WORD during one DMA bus cycle.
AMD Geode™ SC2200 Processor Data Book
For read transfer types, the Core Logic module reads data
from memory and write it to the I/O device associated with
the DMA channel.
For write transfer types, the Core Logic module reads data
from the I/O device associated with the DMA channel and
write to the memory.
The verify transfer type causes the Core Logic module to
execute DMA transfer bus cycles, including generation of
memory addresses, but neither the READ nor WRITE com-
mand lines are activated. This transfer type was used by
DMA Channel 0 to implement DRAM refresh in the original
IBM PC and XT.
DMA Priority
The DMA controller may be programmed for two types of
priority schemes: fixed and rotate (I/O Ports 008h[4] and
0D0h[4] - see Table 6-43 on page 305).
In fixed priority, the channels are fixed in priority order
based on the descending values of their numbers. Thus,
Channel 0 has the highest priority. In rotate priority, the last
channel to get service becomes the lowest-priority channel
with the priority of the others rotating accordingly. This pre-
vents a channel from dominating the system.
The address and WORD Count registers for each channel
are 16-bit registers. The value on the data bus is written
into the upper byte or lower byte, depending on the state of
the internal addressing byte pointer. This pointer can be
cleared by the Clear Byte Pointer command. After this com-
mand, the first read/write to an address or WORD-count
register reads or writes to the low byte of the 16-bit register
and the byte pointer points to the high byte. The next
read/write to an address or WORD-count register reads or
writes to the high byte of the 16-bit register and the byte
pointer points back to the low byte.
When programming the 16-bit channels (Channels 5, 6,
and 7), the address which is written to the base address
register must be the real address divided by two. Also, the
base WORD Count for the 16-bit channels is the number of
16-bit WORDs to be transferred, not the number of bytes
as is the case for the 8-bit channels.
The DMA controller allows the user to program the active
level (low or high) of the DRQ and DACK# signals. Since
the two controllers are cascaded together internally on the
chip, these signals should always be programmed with the
DRQ signal active high and the DACK# signal active low.
DMA Shadow Registers
The Core Logic module contains a shadow register located
at F0 Index B8h (Table 6-29 on page 198) for reading the
configuration of the DMA controllers. This read only regis-
ter can sequence to read through all of the DMA registers.
32580B
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