SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 277

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Core Logic Module - X-Bus Expansion Interface - Function 5
AMD Geode™ SC2200 Processor Data Book
Index 44h-47h
To use F5BAR1, the mask register should be programmed first. The mask register defines the size of F5BAR1 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
Index 48h-4Bh
To use F5BAR2, the mask register should be programmed first. The mask register defines the size of F5BAR2 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
Index 4Ch-4Fh
To use F5BAR3, the mask register should be programmed first. The mask register defines the size of F5BAR3 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
Index 50h-53h
To use F5BAR4, the mask register should be programmed first. The mask register defines the size of F5BAR4 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
Index 54h-57h
To use F5BAR5, the mask register should be programmed first. The mask register defines the size of F5BAR5 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note:
Index 58h
Bit
7:6
5
4
3
2
1
0
Whenever a value is written to this mask register, F5BAR1 must also be written (even if the value for F5BAR1 has not
changed).
Whenever a value is written to this mask register, F5BAR2 must also be written (even if the value for F5BAR2 has not
changed).
Whenever a value is written to this mask register, F5BAR3 must also be written (even if the value for F5BAR3 has not
changed).
Whenever a value is written to this mask register, F5BAR4 must also be written (even if the value for F5BAR4 has not
changed).
Whenever a value is written to this mask register, F5BAR5 must also be written (even if the value for F5BAR5 has not
changed).
Description
Reserved. Must be set to 0.
F5BAR5 Initialized. This bit indicates if F5BAR5 (F5 Index 24h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR5 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR5 is dis-
abled until either this bit is set to 1 or F5BAR5 is written (which causes this bit to be set to 1).
F5BAR4 Initialized. This bit indicates if F5BAR4 (F5 Index 28h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR4 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR4 is dis-
abled until either this bit is set to 1 or F5BAR4 is written (which causes this bit to be set to 1).
F5BAR3 Initialized. This bit indicates if F5BAR3 (F5 Index 1Ch) has been initialized.
At reset this bit is cleared (0). Writing F5BAR3 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR3 is dis-
abled until either this bit is set to 1 or F5BAR3 is written (which causes this bit to be set to 1).
F5BAR2 Initialized. This bit indicates if F5BAR2 (F5 Index 18h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR2 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR2 is dis-
abled until either this bit is set to 1 or F5BAR2 is written (which causes this bit to be set to 1).
F5BAR1 Initialized. This bit indicates if F5BAR1 (F5 Index 14h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR1 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR1 is dis-
abled until either this bit is set to 1 or F5BAR1 is written (which causes this bit to be set to 1).
F5BAR0 Initialized. This bit indicates if F5BAR0 (F5 Index 10h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR0 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR0 is dis-
abled until either this bit is set to 1 or F5BAR0 is written (which causes this bit to be set to 1).
Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued)
F5BAR1 Mask Address Register (R/W)
F5BAR2 Mask Address Register (R/W)
F5BAR4 Mask Address Register (R/W)
F5BAR5 Mask Address Register (R/W)
F5BAR3 Mask Address Register (R/W)
F5BARx Initialized Register (R/W)
32580B
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00h
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