SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 228

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

236
Offset 04h-07h
31:21
Bit
20
19
18
17
16
15
8
7
6
5
4
3
2
1
0
Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Description
IRQ8# Source. Selects the interface source of the IRQ8# signal.
0: ISA - IRQ8# internal signal. (Connected to internal RTC.)
1: LPC - SERIRQ (ball J31).
IRQ7 Source. Selects the interface source of the IRQ7 signal.
0: ISA - IRQ7 (unavailable externally).
1: LPC - SERIRQ (ball J31).
IRQ6 Source. Selects the interface source of the IRQ6 signal.
0: ISA - IRQ6 (unavailable externally).
1: LPC - SERIRQ (ball J31).
IRQ5 Source. Selects the interface source of the IRQ5 signal.
0: ISA - IRQ5 (unavailable externally).
1: LPC - SERIRQ (ball J31).
IRQ4 Source. Selects the interface source of the IRQ4 signal.
0: ISA - IRQ4 (unavailable externally).
1: LPC - SERIRQ (ball J31).
IRQ3 Source. Selects the interface source of the IRQ3 signal.
0: ISA - IRQ3 (unavailable externally).
1: LPC - SERIRQ (ball J31).
Reserved. Must be set to 0.
IRQ1 Source. Selects the interface source of the IRQ1 signal.
0: ISA - IRQ1 (unavailable externally).
1: LPC - SERIRQ (ball J31).
IRQ0 Source. Selects the interface source of the IRQ0 signal.
0: ISA - IRQ0 Internal signal. (Connected to OUT0, System Timer, of the internal 8254 PIT.)
1: LPC - SERIRQ (ball J31).
Reserved.
INTD# Polarity. If LPC is selected as the interface source for INTD# (F0BAR1+I/O Offset 00h[20] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
INTC# Polarity. If LPC is selected as the interface source for INTC# (F0BAR1+I/O Offset 00h[19] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
INTB# Polarity. If LPC is selected as the interface source for INTB# (F0BAR1+I/O Offset 00h[18] = 1), this bit allows signal
polarity selection.
0:
1:
INTA# Polarity. If LPC is selected as the interface source for INTA# (F0BAR1+I/O Offset 00h[17] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
Reserved. Must be set to 0.
IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
Active high.
Active low.
32580B
SERIRQ_LVL — Serial IRQ Level Control Register (R/W)
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC2200 Processor Data Book
Reset Value: 00000000h