PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 15

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

2.2.3
2.2.4
CLOCK SIGNALS
MISCELLANEOUS SIGNALS
Name
S_PERR_L
S_SERR_L
S_REQ_L[8:0]
S_GNT_L[8:0]
S_RESET_L
S_M66EN
S_CFN_L
Name
P_CLK
S_CLKIN
S_CLKOUT[9:0]
Name
Pin #
171
169
9, 8, 7, 6, 5, 4, 3,
2, 207
19, 18, 17, 16, 15,
14, 13, 11, 10
22
153
23
Pin #
45
21
42, 41, 39, 38, 36,
35, 33, 32, 30, 29
Pin #
5
Type
I/OD
Type
Type
STS
TS
O
O
I
I
I
I
I
Description
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received on
the secondary interface. Before being tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system error
condition.
Secondary Request (Active LOW): This is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
Secondary Grant (Active LOW): PI7C8150 asserts this
pin to access the secondary bus. PI7C8150 de-asserts
this pin for at least 2 PCI clock cycles before asserting it
again. During idle and S_GNT_L asserted, PI7C8150
will drive S_AD, S_CBE, and S_PAR.
Secondary RESET (Active LOW): Asserted when any
of the following conditions are met:
1.
2.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, and S_PAR.
Secondary Interface 66MHz Operation: This input is
used to specify if PI7C8150 is running at 66MHz on the
secondary side. When HIGH, the Secondary bus may
run at 66MHz. When LOW, the Secondary bus may
only run at 33MHz.
If P_M66EN is pulled LOW, the S_M66EN is driven
also driven LOW.
Secondary Bus Central Function Control Pin: When
tied LOW, it enables the internal arbiter. When tied
HIGH, an external arbiter must be used. S_REQ_L[0] is
reconfigured to be the secondary bus grant input, and
S_GNT_L[0] is reconfigured to be the secondary bus
request output.
Description
Primary Clock Input: Provides timing for all
transactions on the primary interface.
Secondary Clock Input: Provides timing for all
transactions on the secondary interface.
Secondary Clock Output: Provides secondary clocks
phase synchronous with the P_CLK.
When these clocks are used, one of the clock outputs
must be fed back to S_CLKIN. Unused outputs may be
disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins and
MSK_IN
3. Terminating them electrically.
Description
Signal P_RESET_L is asserted.
Secondary reset bit in bridge control register in
configuration space is set.
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150