PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 22

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

3.4
3.5
3.5.1
Table 4-2. Write Transaction Forwarding
PI7C8150 always performs positive address decoding (medium decode) when accepting
transactions on either the primary or secondary buses. PI7C8150 never does subtractive
decode.
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases.
A data phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted.
A transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the
same PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is
de-asserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L
are asserted. See Section 4.8 for further discussion of transaction termination.
Depending on the command type, PI7C8150 can support multiple data phase
PCI transactions. For detailed descriptions of how PI7C8150 imposes disconnect
boundaries, see Section 3.5.4 for write address boundaries and Section 3.6.3 read address
boundaries.
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions.
Table 4–2 shows the method of forwarding used for each type of write operation.
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C8150 determines that a memory write transaction is to be forwarded across the
bridge, PI7C8150 asserts DEVSEL_L with medium timing and TRDY_L
in the next cycle, provided that enough buffer space is available in the posted memory
write queue for the address and at least one DWORD of data. Under
this condition, PI7C8150 accepts write data without obtaining access to the target bus. The
PI7C8150 can accept one DWORD of write data every PCI clock cycle.
That is, no target wait state is inserted. The write data is stored in an internal
posted write buffers and is subsequently delivered to the target.
The PI7C8150 continues to accept write data until one of the following events occurs:
!
!
Type of Transaction
Memory Write
Memory Write and Invalidate
Memory Write to VGA memory
I/O Write
Type 1 Configuration Write
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an
aligned 4KB boundary, depending on the transaction type.
12
Type of Forwarding
Posted (except VGA memory)
Posted
Delayed
Delayed
Delayed
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150