PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 8

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Table 4-5. Read Transaction Prefetching_________________________________________________ 17
Table 4-6. Device Number to IDSEL S_AD Pin Mapping____________________________________ 21
Table 4-7. Delayed Write Target Termination Response _____________________________________ 25
Table 4-8. Response to Posted Write Target Termination ____________________________________ 26
Table 4-9. Response to Delayed Read Target Termination ___________________________________ 27
Table 5-1. Summary of Transaction Ordering _____________________________________________ 36
Table 6-1. Setting the Primary Interface Detected Parity Error Bit ____________________________ 44
Table 6-2. Setting Secondary Interface Detected Parity Error Bit______________________________ 45
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit_____________________ 45
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit ___________________ 46
Table 6-5. Assertion of P_PERR#_______________________________________________________ 46
Table 6-6. Assertion of S_PERR# _______________________________________________________ 47
Table 6-7. Assertion of P_SERR# for Data Parity Errors ____________________________________ 47
Table 10-1. GPIO Operation ___________________________________________________________ 56
Table 10-2. GPIO Serial Data Format ___________________________________________________ 57
Table 11-1. Power management transitions _______________________________________________ 58
Table 16-1. TAP Pins_________________________________________________________________ 85
Table 16-2. JTAG Boundary Register Order _______________________________________________ 87
LIST OF FIGURES
Figure 9-1. Secondary Arbiter Example...................................................................................................... 53
Figure 16-1. Test Access Port Block Diagram ............................................................................................ 84
Figure 17-1. PCI Signal Timing Measurement Conditions ......................................................................... 91
Figure 18-1. 208-pin FQFP Package Outline ............................................................................................... 92
Figure 18-2. 256-ball PBGA Package Outline ............................................................................................. 93
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March 19, 2003 – Revision 1.04