PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 75

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

14.1.5
14.1.6
14.1.7
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
CACHE LINE SIZE REGISTER – OFFSET 0Ch
20
21
22
23
24
26:25
27
28
29
30
31
Bit
7:0
Bit
15:8
23:16
31:24
Capabilities List
66MHz Capable
Reserved
Fast Back-to-
Back Capable
Data Parity Error
Detected
DEVSEL_L
timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity
Error
Function
Revision
Function
Programming
Interface
Sub-Class Code
Base Class Code
R/O
R/O
R/O
R/O
R/WC
R/O
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
Type
R/O
R/O
R/O
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
Reset to 1
Set to 1 when P_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
DEVSEL_L timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
Set to 1 when P_SERR_L is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
Description
Indicates revision number of device. Hardwired to 01h
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
65
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150