PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 78

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

14.1.17
14.1.18
14.1.19
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
26:25
27
28
29
30
31
Bit
3:0
15:4
Bit
19:16
31:20
Bit
DEVSEL_L
timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Received System
Error
Detected Parity
Error
Function
Memory Base
Address [15:4]
Function
Memory Limit
Address [31:20]
Function
R/O
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
R/W
Type
R/O
R/W
Type
Description
DEVSEL# timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary interface
are terminated with Master Abort
Reset to 0
Set to 1 when S_SERR_L is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary interface
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
68
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150