PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 16

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

2.2.5
2.2.6
GENERAL PURPOSE I/O INTERFACE SIGNALS
JTAG BOUNDARY SCAN SIGNALS
MSK_IN
P_VIO
S_VIO
BPCCE
CFG66
SCAN_EN_H
MS0, MS1
Name
GPIO[3:0]
Name
TCK
TMS
TDO
126
124
135
44
125
125
155, 106
Pin #
24, 25, 27, 28
Pin #
133
132
130
6
Type
Type
TS
O
I
I
I
I
I
I
I
I
I
Secondary Clock Disable Serial Input: This pin is used
by PI7C8150 to disable secondary clock outputs. The
serial stream is received by MSK_IN, starting when
P_RESET is detected deasserted and S_RESET_L is
detected as being asserted. The serial data is used for
selectively disabling secondary clock outputs and is
shifted into the secondary clock control configuration
register. This pin can be tied LOW to enable all
secondary clock outputs or tied HIGH to drive all the
secondary clock outputs HIGH.
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus. P_VIO
must be tied to 3.3V only when all devices on the
primary bus use 3.3V signaling. Otherwise, P_VIO is
tied to 5V.
Secondary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the secondary bus.
S_VIO must be tied to 3.3V only when all devices on the
secondary bus use 3.3V signaling. Otherwise, S_VIO is
tied to 5V.
Bus/Power Clock Control Management Pin: When
this pin is tied HIGH and the PI7C8150 is placed in the
D3
secondary bus in the B2 power state. The secondary
clocks are disabled and driven to 0. When this pin is tied
LOW, there is no effect on the secondary bus clocks
when the PI7C8150 enters the D3
66MHz Configuration: This pin is used to designate
66MHz operation. Tie HIGH to enable 66MHz operation
or tie LOW to designate 33MHz operation.
Full-Scan Enable Control: When SCAN_EN_H is
LOW, full-scan is in shift operation. When
SCAN_EN_H is HIGH, full-scan is in parallel operation.
Note: Valid only in test mode. Pin is CFG66 in normal
operation.
Mode Selection: Reserved for future features.
MS0: 0, MS1: 0 – RESERVED
MS0: 0, MS1: 1 – RESERVED
MS0: 1, MS1: x – Intel compatible (default)
Description
General Purpose I/O Data Pins: The 4 general-purpose
signals are programmable as either input-only or bi-
directional signals by writing the GPIO output enable
control register in the configuration space.
Description
Test Clock. Used to clock state information and data
into and out of the PI7C8150 during boundary scan.
Test Mode Select. Used to control the state of the Test
Access Port controller.
Test Data Output. When SCAN_EN_H is HIGH, it is
used (in conjunction with TCK) to shift data out of the
Test Access Port (TAP) in a serial bit stream.
HOT
power state, it enables the PI7C8150 to place the
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
HOT
power state.
PI7C8150