PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 62

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

8.1
8.2
8.2.1
PI7C8150 must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to PI7C8150,
typically on the motherboard. For the secondary PCI bus, PI7C8150 implements an internal
arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This
chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
PI7C8150 implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L,
for primary PCI bus arbitration. PI7C8150 asserts P_REQ_L when forwarding transactions
upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending
transaction resides in the queues in the upstream direction, either posted write data or
delayed transaction requests, PI7C8150 keeps P_REQ_L asserted. However, if a target
retry, target disconnect, or a target abort is received in response to a transaction initiated by
PI7C8150 on the primary PCI bus, PI7C8150 de-asserts P_REQ_L for two PCI clock
cycles.
For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has
been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter
after PI7C8150 has asserted P_REQ_L, PI7C8150 initiates a transaction on the primary bus
during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8150 when P_REQ_L
is not asserted, PI7C8150 parks P_AD, P_CBE, and P_PAR by driving them to valid logic
levels. When the primary bus is parked at PI7C8150 and PI7C8150 has a transaction to
initiate on the primary bus, PI7C8150 starts the transaction if P_GNT_L was asserted
during the previous cycle.
SECONDARY PCI BUS ARBITRATION
PI7C8150 implements an internal secondary PCI bus arbiter. This arbiter supports eight
external masters on the secondary bus in addition to PI7C8150. The internal arbiter can be
disabled, and an external arbiter can be used instead for secondary bus arbitration.
SECONDARY BUS ARBITRATION USING THE INTERNAL
ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied
LOW. PI7C8150 has nine secondary bus request input pins, S_REQ_L[8:0], and has nine
secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus
masters.
The secondary bus request and grant signals are connected internally to the arbiter and are
not brought out to external pins when S_CFN_L is HIGH.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each
set taking care of 9 requests / grants. Each set of masters can be assigned to a high priority
group and a low priority group. The low priority group as a whole represents one entry in
the high priority group; that is, if the high priority group consists of n masters, then in at
least every n+1 transactions the highest priority is assigned to the low priority group.
Priority rotates evenly among the low priority group. Therefore, members of the high
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150