PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 49

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

6.2
6.2.1
6.2.2
When PI7C8150 detects an address parity error on the secondary interface, the following
events occur:
!
!
!
DATA PARITY ERRORS
When forwarding transactions, PI7C8150 attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8150.
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8150 detects a data parity error during a Type 0 configuration write transaction
to PI7C8150 configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8150 asserts
P_TRDY_L and writes the data to the configuration register. PI7C8150 also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8150 does not assert
P_PERR_L.
PI7C8150 sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
READ TRANSACTIONS
When PI7C8150 detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L.
For downstream transactions, when PI7C8150 detects a read data parity error on the
secondary bus, the following events occur:
If the parity error response bit is set in the bridge control register, PI7C8150 does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150 proceeds normally
and accepts transaction if it is directed to or across PI7C8150.
PI7C8150 sets the detected parity error bit in the secondary status register.
PI7C8150 asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
!
!
!
The parity error response bit is set in the command register.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
39
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150