PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 37

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

3.8.4
3.8.4.1
Table 4-9. Response to Delayed Read Target Termination
!
PI7C8150 makes 2
After PI7C8150 makes 2
target bus, PI7C8150 asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
command register for secondary bus) and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8150 will report system error. See Section 6.4 for a description of system error
conditions.
TARGET TERMINATION INITIATED BY PI7C8150
PI7C8150 can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
TARGET RETRY
PI7C8150 returns a target retry to the initiator when it cannot accept write data or return
read data as a result of internal conditions. PI7C8150 returns a target retry to an initiator
when any of the following conditions is met:
For delayed write transactions:
!
!
!
!
!
!
!
!
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C8150 receives a target abort.
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Target response has been received but has not progressed to the head of the return
queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8150, and the write transaction is
not a locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
24
(default) read attempts resulting in a response of target retry.
24
Response
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
(default) attempts of the same delayed read transaction on the
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150