S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 11

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CSU Ref. Clock (REFCLKAP/N) –
External Pin
The differential CML Reference Clock (REFCLKAP/N
by default) input is used to drive the clock synthesizer
Phase Lock Loop (PLL). See Table 3, Reference
Frequency (CSU REFCLK) for the Clock Synthesis
Unit and for the recommended FEC rates. The
REFCLKAP/N input may go into the Phase Detector
(PD) block shown in Figure 5. The output of the PD
block (PD_UP/PD_DOWN) can be fed into an External
filter and Voltage Controlled Oscillator (VCO) to clean
up the REFCLKAP/N for improved jitter generation.
The output of the external VCO is fed into the CSU_IN
input. The CSU_IN will act as the reference clock for
the CSU block if XVCO select input is active. Table 3
summarizes
required for FEC/10GbE/10G FC operation. The
S19252
requirements needed for the FEC applications that
provide up to eight bytes of correction for a 255 byte
block. Increased CSU REFCLK frequency is required
for bandwidth expansion due to code words and Frame
Synchronization Byte (FSB). This input is internally
biased and terminated and must be AC coupled.
External Voltage Controlled Oscillator
(XVCO) – Register
The XVCO is the active high control input that selects
CSU_IN as the reference clock for the CSU block.
When active, the CSU_IN (output of the external VCO)
input is used as the reference clock for the CSU for
improved jitter generation. When inactive and in the
normal mode, the CSU_REFCLK is directly used as
the reference clock for the CSU block. This input is only
accessible through the serial bus register.
Transmitter Reset (TX_RSTB) –
Register
The active low Transmitter Reset (TX_RSTB) signal,
when asserted low, will reset the CSU and associated
logic. Use this reset after all Transmitter CSU and
REFCLK control changes. When this bit is high
(default) the CSU will function normal. This input is only
accessible through the serial bus register.
Revision 5.03
incorporates
the
increased
the
AppliedMicro - Confidential and Proprietary
bandwidth
CSU_REFCLK
expansion
rates
External Voltage Controlled Oscillator
155 MHz (XVCO155) – Register
The XVCO155 is the active high control for selecting
either a 622 MHz (or equiv. FEC/10 GbE/10 GFC) or
155 MHz (or equiv. FEC/10 GbE/10 GFC) external
VCO Frequency. When this bit is low (default), the
XVCO operates at 622 MHz. When this bit is high, the
XVCO operates at 155 MHz. This input is only
accessible through the serial bus register.
Kill Transmitter 155MCK Clock Output
(KILLTXMCK) – Register
The active high Kill Transmitter 155MCK clock output
(KILLTXMCK) signal, when asserted high, will force the
TX_155MCK clock output to a logic state determined
by the CLKSTOP_VAL. When this bit is low (default)
the TX_155MCK will function normal. This input is only
accessible through the serial bus register.
Kill Transmitter PCLK Output Clock
(KILLPCLK) – Register
The active high Kill Transmitter PCLK output clock
(KILLPCLK) signal, when asserted high, will force the
PCLK clock output to a logic state determined by the
CLKSTOP_VAL. When this bit is low (default) the
PCLK will function normal. This input is only accessible
through the serial bus register.
Kill Transmit Serial Data Output
(KILLTXDATB) – Register
The active low Kill Transmitter Serial Data output
(KILLTXDATB) signal, when asserted low, will force the
TSD data output pins to a logic state determined by the
TSD_SQ_POL. When this bit is high (default) the TSD
output will function normal. This input is only accessible
through the serial bus register.
S19252 Data Sheet
11