S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 27

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The user defined pattern can be loaded through the
BIST_PTRN[15:0] register. There are two modes of
transmit BIST operation:
When the diagnostic loopback mode is not active, the
serial output data (TSDP/N) must be looped back into
the serial input (SERDATIP/N) for the transmit PRBS
checker to work with the transmit PRBS generator. If
the diagnostic loopback mode is enabled, the TSDP/N
outputs will be internally looped back into the
SERDATIP/N inputs.
Once the TX_BIST_EN input is programmed to logic
high, the transmit PRBS checker will be activated but
will not start checking for the valid data pattern until
RX_LOCKDET is active. This will ensure that valid data
is being passed through the receive channel. Once the
RX_LOCKDET is active, the checker will begin its
initialization phase for 15 CRU_REFCLK cycles. The
transmit checker reads the parallel data output and
figures out the next PRBS pattern in the initialization
phase. After the checker is initialized, it will compare
the parallel data output with the calculated pattern. If
the parallel data output does not match the calculated
pattern, the TX_BIST_ERR flag will be set active and
the number of errors will start accumulating on the
BER_COUNT[11:0] register. The bit error rate range
can be selected with the appropriate setting of the
BER_SELECT[2:0]. See Table 14 for details of setting
the range for bit error rate.
The TX_BIST_ERR flag can be cleared by asserting
TX_BIST_CLR in the TX_BIST_EN mode or by
resetting (RSTB) the S19252. Once the TX_BIST_CLR
signal has been received by the checker, it will go back
to the initialization phase. TX_BIST_CLR is an active
high level sensitive input. In order for the checker to
clear the TX_BIST_ERR flag, the TX_BIST_CLR must
be asserted high.
Also the BER_RSTB input register resets the
BER_COUNT[11:0]
BER_RSTB is a active high input. When active
BER_COUNT[11:0] is not reset after each terminal
count, but instead continues to accrue errors. When
inactive, BER_COUNT[11:0] is reset to zero error value
after each terminal count. The TERM_COUNT output
monitors for the terminal count of the PRBS checker.
The terminal count is set by the BER_SELECT[2:0]
register. See Table 14 for details. Each transition of
TERM_COUNT signal indicates that the terminal count
Revision 5.03
1. Normal operation with DLEB disabled
2. Normal operation with DLEB enabled
after
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each
terminal
count.
has been reached. This signal is initially set low upon
RSTB
activated. The TERM_COUNT makes a low to high
transition when the first terminal count is reached. A
transition
BER_COUNT[11:0] register to zero depending upon
the BER_RSTB setting. When BER_RSTB is active
(high), BER_COUNT[11:0] is not reset after each
terminal count, but instead continues to accrue errors.
The BER_OVERFLOW output will indicate if the
BER_COUNT[11:0]
BER_OVERFLOW goes active, the bit error rate range
select (BER_SELECT[2:0]) needs to be changed. This
signal is active high and is latched high. This signal
monitors the RX checker count when the RX_BIST_EN
is active and TX checker count when TX_BIST_EN is
active.
Receiver Functional Description
The S19252 transceiver chip provides the first stage of
the digital processing of a receive SONET STS-192/10
Gigabit Ethernet bit-serial stream. It converts the 9.953
Gbps bit-serial data stream into a 622.08 Mbps 16-bit
parallel data format (or equivalent FEC/10 Gigabit
Ethernet rates).
Post-Amp
The S19252 limiting Post-Amp takes the differential
serial data from the SERDATIP/N pins and provides 36
dB small-signal gain. The input to the Post Amp can be
either AC or DC coupled. There is an offset voltage
adjustment (PAOFFADJ[9:0]) for DC coupling in order
to facilitate duty cycle distortion correction.
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 5, Transceiver Functional Block Diagram,
generates a clock that is the same frequency as the
incoming data bit rate at the serial data input. The clock
is phase aligned by a PLL so that it samples the data in
the center of the data eye pattern.
The
synchronous signal from the serial data input using a
frequency and Phase Lock Loop (PLL). The PLL
consists of a Voltage Controlled Oscillator (VCO),
Phase/Frequency Detectors (PFD), and a loop filter.
Clock
or
on
when
Recovery
TERM_COUNT
TX_BIST_EN/RX_BIST_EN
has
Unit
overflowed.
(CRU)
S19252 Data Sheet
will
When
extracts
set
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