S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 26

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
FIFO
A FIFO is added to decouple the internal and external
parallel clocks. The internally generated divide-by-16
clock (PCLK) is used to clock out data from the FIFO.
PHINIT and TX_LOCKDET are used to center or reset
the FIFO. The PHINIT and TX_LOCKDET signals will
center the Figure 28 FIFO once they have been
asserted (high). (See Figure 28, FIFO Initialization).
This is in order to ensure that PICLK is stable. This
scheme allows the user to have an infinite PCLK-to-
PICLK delay through the ASIC. Once the FIFO is
centered, the PCLK-to-PICLK delay can have a
maximum drift as specified in Table 36, Transmitter
Timing Characteristics.
The FIFO shown in Figure 5, Transceiver Functional
Block Diagram, is comprised of two sets of registers.
The
Ethernet rate) clocks in the data from the PINP/N[15:0]
bus to the first register of the FIFO. A second register is
a parallel loadable shift register which takes its parallel
input from the first register.
An internally generated PCLK clock, which is phase
aligned to the transmit serial clock, activates the
parallel data transfer between registers. This 16-bit
data is fed into the parallel-to-serial converter.
FIFO Initialization
The FIFO can be initialized in one of the following three
ways:
During normal running operation, the incoming data is
passed from the PICLK timing domain to the internally
generated divide-by-16 clock timing domain. Although
the frequency of PICLK and the internally generated
clock (PCLK) are the same, their phase relationship is
26
1. During power up, once the PLL has locked to the
2. When RSTB goes active, the entire transmitter is
3. When AUTO_FIFO_INIT is not enabled, the user
reference clock provided on the CSU_REFCLK
pins, the TX_LOCKDET will go active and initial-
ize the FIFO.
reset. This causes the PLL to go out of lock, thus
the TX_LOCKDET goes inactive. When the PLL
reacquires the lock, the TX_LOCKDET goes
active and initializes the FIFO. Note that PCLK is
held in reset when RSTB is active.
can also initialize the FIFO by raising PHINIT
input.
622.08 MHz
(or
equivalent
AppliedMicro - Confidential and Proprietary
FEC/10 Gigabit
arbitrary. To prevent errors caused by short setup or
hold times between the two timing domains, the FIFO
circuitry monitors the phase relationship between
PICLK and the internally generated clock. When a
potential setup or hold time violation is detected, Phase
Error (PHERR) goes high. If the condition persists,
PHERR will remain high. When AUTO_FIFO_INIT is
not enabled, if PHERR conditions occur, PHINIT
should be activated to recenter the FIFO. If
AUTO_FIFO_INIT is enabled, PHERR is connected to
PHINIT internally. Then, the FIFO is centered
automatically. PHERR will go inactive when the
realignment is complete or the drift has fallen to a level
within the specified maximum of 2 ns. (See Figure 28
FIFO Initialization.)
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 5,
Transmitter Functional Block Diagram, is comprised of
staged registers and 2:1 multiplexers. The 16-bit wide
data output from the FIFO is presented to the first
register/2:1 multiplexer and converted from 16 bits to 8
bits wide. This procedure is repeated to convert to 4, 2
and finally 1-bit wide serial data.
Duo-Binary Encoding
The S19252 has a built-in duobinary encoder.
Duobinary coding is a means of controlling ISI by
adding the input with the previous data bit. Pre-coding
increases duobinary coding’s performance by summing
(modulo-2) the previous pre-coded input with the
current input prior to the final summing operation. The
duo-binary precoder is implemented on the parallel
side to save power. This function is controlled by
setting the DUO_BINARY_EN register bit through the
serial interface.
Transmit Built-In Self Test Mode
The S19252 circuitry includes a PRBS generator and a
checker. The transmit built-in self test allows for the
verification of the serial data path, CRU, CSU and most
of the other blocks in the S19252. The S19252 goes in
the transmit BIST mode when TX_BIST_EN is
programmed to logic high.
Once the S19252 is in the transmit BIST mode, the
PRBS generator will start sending the pattern through
the parallel input data path. The pattern can be a PRBS
pattern or a user defined pattern depending upon the
PRBS_SELECT[1:0] settings. See Table 13 for details.
Revision 5.03