S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 28

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
The frequency detector ensures predictable lock
conditions. It is used during acquisition and serves as a
means to pull the VCO into the range of the data rate
where the phase detector is capable of acquiring lock.
The phase detector used in the CRU is designed to
give minimum static phase error of the PLL. When a
transition has occurred, the value of the sample in the
vicinity of the transition indicates whether the VCO
clock leads or lags the incoming data, and the phase
detector produces a binary output accordingly.
When a loss of signal condition exists, the PLL locks
onto
(CRU_REFCLK) to provide a steady output clock.
There are two pins (RXCAP1 and RXCAP2) to connect
the external capacitor and resistors in order to adjust
the PLL loop performance.
The phase relationship between the edge transitions of
the data and those of the generated clock are
compared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integrating loop filter. The output of the
loop filter controls the frequency of the Voltage
Controlled Oscillator (VCO), which generates the
recovered clock.
Frequency
guaranteed
(CRU_REFCLK) onto which the PLL locks when data
is lost. If the frequency of the incoming signal varies by
a value greater than that stated in Table 27, with
respect to CRU_REFCLKP/N, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The assertion of Loss-of-Signal (LOS_SD) output or
de-assertion of Signal-Detect (LOS_SD) input will also
cause an out-of-lock condition.
The loop filter transfer function is optimized in order to
enable the PLL to track the jitter yet tolerate the
minimum transition density expected in a received
SONET or 10 Gigabit Ethernet data signal.
The total loop dynamics of the clock recovery PLL yield
a jitter tolerance which exceeds the minimum tolerance
proposed for SONET equipment by the Telecordia
standard.
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AppliedMicro - Confidential and Proprietary
incoming
reference
reference
data
clock
input
is
Receive Lock Detect
The S19252 contains a lock detect circuit that monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss-of-signal or loss-of-lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the typical
value stated in Table 27, Performance Specifications,
the PLL will be declared out of lock. The lock detect
circuit will poll the input data stream in an attempt to
reacquire lock to data. If the recovered clock frequency
is determined to be within the typical value stated in
Table 27, Performance Specifications, the PLL will be
declared in lock and the lock detect output will go
active. An inactive LOS_SD input will also cause an
out-of-lock condition. The receive lock detect output
should not be used as a frequency discriminator for out
of band signals.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 16-bit
registers. The first is a serial-in, parallel-out shift
register, which performs serial-to-parallel conversion.
The second is a 16-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries. On the falling edge of the POCLK, the
data in the holding register is transferred to an output
holding register which drives POUTP/N[15:0].
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
low, a loopback from the transmitter to the receiver at
the serial data rate can be set up for diagnostic
purposes. The differential serial output data from the
transmitter is routed to the CRU block in place of the
normal data stream (RSD). The Transmit Serial Data
Output TSDP/N is accessible in the DLEB mode. DLEB
takes precedence over LOS_SD.
Revision 5.03