S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 22

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
In the RLPTIME mode, the internal POCLK is fed into
the phase detector block. The output of the phase
detector block is fed into the external VCO. The output
of the external VCO then goes into the CSU_IN input
which acts as the reference clock for the internal clock
Table 12: Reference and Loopback Enable
The BOLD CELLS denote the default state
22
DLEB
X
0
0
0
0
1
1
1
1
1
1
LLEB
0
0
X
1
1
0
0
1
1
1
1
RLPTIME
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X
1
1
0
0
0
0
0
0
1
1
XVCO
X
X
X
0
1
0
1
0
1
1
0
Not a Valid Mode
Not a Valid Mode
Not a Valid Mode
DLEB
DLEB/XVCO with TXREFCLK
LLEB with CSU timed to RSD recovered clock
LLEB + XVCO timed to RSD recovered clock
Normal Mode
Normal Mode/XVCO with TXREFCLK
Normal Mode/XVCO timed to RSD recovered clock
Normal Mode/RLPTIME timed to RSD recovered clock
synthesizer circuit (CSU block in Figure 5). The jitter
transfer specification, as defined in GR-253-CORE, is
met in this mode. See Table 12, Reference and
Loopback Enable, for details. This input is only
accessible through the serial bus register.
Mode/ Timing Source
Revision 5.03