S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 38

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Sinusoidal Jitter
The Sj applied for tolerance testing is defined by the
jitter mask shown in Figure 10 and Table 18 (per IEEE
802.3ae). The Loop Bandwidth (LB) for S19252 is
approximately 8 MHz.
Test Pattern
Test pattern is chosen per IEEE 802.3ae Section
52.9.1. The test pattern is a static pattern and can be
loaded into a BERT. IEEE 802.3ae specifies two
pseudo-random test patterns for 10GBASE-ER testing.
One pattern represents typical scrambled data while
the other represents a less typical pattern which could
Figure 9:
38
Input Jitter Mask for Receiver Test
10
10
10
10
-10
-12
-6
-8
AppliedMicro - Confidential and Proprietary
Any Points in the "Open Eye" Region
Fail Transmit BERT Mask
Unit Interval (UI)
Eye Opening
at 10
happen by chance and is thought to be more
demanding of the transmission process including the
clock recovery sub-system. Both patterns are balanced
over their length of 33792 bits.
Test pattern is constructed from 4 Segments
•
•
•
•
•
0.5
-12
BER
1 segment is constructed with 128 Blocks
1 block is 2 Sync Bits and 64 Payload Bits
Pay load bits are generated with the scrambler
shown in Figure 11.
Scrambler seeded per Tables 19 and 20.
Data input is set to 1 or 0.
Revision 5.03