PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 14

• Manufacturer Part Number: PCI-BOARD/S25
• Manufacturer: Altera

Specifications of PCI-BOARD/S25

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Stratix PCI Development Board Data Sheet
Note:
(1)
(2)
(3)
(4)
14
B1B_RX_CLKn
B1B_RX_CLKp
DDR_CLK_FBIN
CLK_25MHZ
DDR_CLK0n
DDR_CLK0p
DDR_CLK1n
DDR_CLK1p
DDR_CLK2n
DDR_CLK2p
DDR_CLK_FBOUT
CLK_TO_SCRUZ
Table 9. Stratix Input Clocks
Table 10. Stratix Output Clocks (Part 1 of 2)
Signal Name
Signal Name
A global clock input can feed Stratix high-speed PLLs directly. This table shows the direct connections and does not
show the connection via global clock networks.
PLL7 through PLL12 are not available in the EP1S25 device. Therefore, they are only available in the Professional
Board.
To use different PLLs within the Stratix device, the designer can drive the CLK_OSC_A signal to different input clock
pins on the Stratix device by installing different resistors. The value shown in this table is the factory default setting.
See page 15 of the board schematics for complete details on the various options available for the board.
To use different PLLs within the Stratix device, the designer can drive the CLK_OSC_B signal to different input clock
pins on the Stratix device by installing different resistors. The value shown in this table is the factory default setting.
See page 15 of the board schematics for complete details on the various options available for the board.
HSDI port B Connectors (J9.49, J8.112) Stratix device (U2.AB29)
HSDI port B Connectors (J9.47, J8.114) Stratix device (U2.AB28)
Stratix device (D18)
On-Board 25-MHz 10/100 Ethernet
Oscillator (OSC1.4))
Stratix Source Pin
SMA Clock Input Requirements
The SMA clock input CLK_SMA can be provided by an external signal
source through the connector J16. Use a 50- signal source and cable with
an LVTTL-type signal (square-wave, with a voltage swing from 0.0 to
+3.3 V). The maximum frequency of this input is 422 MHz.
Stratix Output Clocks
Table 10
U2.AL16
U2.A16
U2.B16
U2.A17
U2.B17
U2.A18
U2.B18
U2.D18
(Part 2 of 2)
Source
lists the Stratix output clocks and their distribution on the board.
Stratix PLL
PLL5
PLL5
PLL5
PLL5
PLL5
PLL5
PLL5
PLL6
Stratix device (U2.D17)
Ethernet MAC/PHY device
(U11.127)
DDR SDRAM Memory Connector (J10.37)
DDR SDRAM Memory Connector (J10.35)
DDR SDRAM Memory Connector (J10.158)
DDR SDRAM Memory Connector (J10.160)
DDR SDRAM Memory Connector (J10.91)
DDR SDRAM Memory Connector (J10.89)
Stratix device (U2.D17)
Expansion Prototype Card (PROTO1) (J4.11)
Destination
Destination
Altera Corporation
PLL8
PLL5 FB
N/A
Primary PLL Used
Notes
(1),
(2)