PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 73
PCI-BOARD/S25
Manufacturer Part Number
PCI-BOARD/S25
Description
Manufacturer
Altera
Datasheet
1.PCI-BOARDS25.pdf
(76 pages)
Specifications of PCI-BOARD/S25
Lead Free Status / Rohs Status
Supplier Unconfirmed
E
D
C
B
A
3.3V
3.3V
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
C236
0.1uF
X7R
(place near socketed oscillators)
C239
0.1uF
X7R
C237
0.01uF
X7R
C240
0.01uF
X7R
8
8
TP18
Configuration / System Clock
C238
1.0uF
X7R
C241
1.0uF
X7R
(socketed half-can oscillator)
(socketed half-can oscillator)
2
3
(external clock source)
1
8
1
8
High-Speed Clock
SMA Connector
J16
1053378-1
GND1
GND2
J14
1108800
(Default = 33 MHz)
J15
1108800
(Default = 100 MHz)
NC
VDD
NC
VDD
OUTPUT
OUTPUT
Output
GND3
GND4
GND
GND
5
4
5
4
4
1
5
7
7
BOARDS IN CHAIN
DOUBLE (w/bank 1)
DOUBLE (w/bank 1)
SINGLE (default)
R114
50
CLK_OSC_B
JTAG_CONN_TDO 17
JTAG_MAX_TDI 17
JTAG_CONN_TDI
CLK_SMA
JTAG BYPASS JUMPERS
CLK_OSC_A
6
6
POSITION
NEAR
1
3
5
-n/a-
FAR
J17
CON6A
CLK_SMA
CLK_SMA
Clocking, JTAG Bypass Jumper
CLK_OSC_B
CLK_OSC_B
CLK_OSC_B
CLK_OSC_B
2
4
6
14,17
Also drives MAX3256A for configuration and
Santa Cruz Daughtercard for potential use on
a daughtercard. AC termination on sheet 14.
SHUNT ONE
PIN1-PIN3
PIN1-PIN3
PIN3-PIN5
10,17
10
CLK_OSC_A
JTAG_SAMTEC_TDO
17
R103
R110
R108
R113
JTAG_STRATIX_TDO
JTAG_CONN_TDI
CLK_OSC_A
CLK_OSC_A
CLK_OSC_A
5
5
SHUNT TWO
PIN4-PIN6
PIN2-PIN4
PIN2-PIN4
30
30
30
30
R106
R111
R112
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
30
30
30
DDR_CLK_FBIN
DDR_CLK_FBIN
4
4
B1_REF_CLK_IN 10
B1A_RX_CLKn 10,11
B1A_RX_CLKp 10,11
LPCI_TRDYn 3,4
LPCI_CLK 3,4
B6_RX_CLKn 11
B6_RX_CLKp 11
B6_REF25_CLK 16
CLK_FROM_SCRUZ 14
B1B_RX_CLKn 10
B1B_RX_CLKp 10
B6_REF60_CLK 16
PLL_ENA 16
CLK_SMA
CLK_OSC_B_PLL2
CLK_OSC_A_PLL6
CLK_OSC_B_PLL6
CLK_SMA
CLK_OSC_B_PLL3
CLK_OSC_A_PLL4
CLK_OSC_A_PLL5
CLK_OSC_B_PLL5
LPCI_RSTn 3,4
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
AM19
AM15
AM17
AK19
AK15
AB29
AB28
AF19
AL19
AJ19
AJ15
AL15
AL17
AB4
AB5
T30
T29
T28
T27
U32
U31
U30
U29
A15
B15
C15
D15
B19
A19
D19
C19
L28
L29
C17
D17
U3
U4
U1
U2
T5
T6
T3
T4
L5
L4
B1A_RX_CLKp
B1B_RX_CLKp
B6_RX_CLKp
U2J
EP1S40F1020
CLK0n
CLK0p
CLK1n
CLK1p
CLK2n
CLK2p
CLK3n
CLK3p
CLK4n
CLK4p
CLK5n
CLK5p
CLK6n
CLK6p
CLK7n
CLK7p
CLK8n
CLK8p
CLK9n
CLK9p
CLK10n
CLK10p
CLK11n
CLK11p
CLK12n
CLK12p
CLK13n
CLK13p
CLK14n
CLK14p
CLK15n
CLK15p
FPLL8CLKn
FPLL8CLKp
FPLL7CLKn
FPLL7CLKp
FPLL10CLKn
FPLL10CLKp
FPLL9CLKn
FPLL9CLKp
PLL_ENA
PLL5_FBn
PLL5_FBp
PLL6_FBn
PLL6_FBp
Differential input termination resistors for
High-Speed Bank 1 and Bank 6 clock inputs.
3
3
PLL1
PLL2
PLL6
PLL12
PLL3
PLL7
PLL7
PLL9
PLL4
PLL11
PLL5
PLL10
PLL8
PLL7
PLL9
R97
R98
R99
PLL10
PLL5_OUT0n
PLL5_OUT0p
PLL5_OUT1n
PLL5_OUT1p
PLL5_OUT2n
PLL5_OUT2p
PLL5_OUT3n
PLL5_OUT3p
PLL6_OUT0n
PLL6_OUT0p
PLL6_OUT1n
PLL6_OUT1p
PLL6_OUT2n
PLL6_OUT2p
PLL6_OUT3n
PLL6_OUT3p
Title
Size
Date:
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Stratix PCI Development Board
B
100
100
100
Document Number
Wednesday, February 12, 2003
B1A_RX_CLKn
B1B_RX_CLKn
B6_RX_CLKn
A16
B16
A17
B17
A18
B18
C18
D18
AM16
AL16
AK16
AJ16
AK17
AJ17
AM18
AL18
2
2
Note: DDR_CLK_FB fed into upper bank pin to be
designated for generation of the strobe skew
delays. CLK12p pin should be designated for
DQS shifting. (Clock Input Pin B15)
Note: DDR_CLK_FB can be used for board-level
de-skew of DDR clocks between the internal
Stratix registers and the DDR SO_DIMM's
memory. (Clock Input Pin C17)
DDR_CLK_FBOUT
6
6
6
6
6
6
R101
R102
R104
(DD_CLK_FBOUT/DDR_CLK_FBIN)
DDR_CLK0n
DDR_CLK0p
DDR_CLK1n
DDR_CLK1p
DDR_CLK2n
DDR_CLK2p
PLL5 Output Vcc = 2.5V
PLL6 Output Vcc = 3.3V
150-0216200-01
50
50
50
14
10
17
R251
CLK_TO_SCRUZ
B1_REF_CLK_OUT
CLK_TO_MAX_A
Sheet
50
15
DDR_CLK_FBIN
1
1
o f
18
R e v
B
E
D
C
B
A