PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 4

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PCI-BOARD/S25

Manufacturer Part Number
PCI-BOARD/S25
Description
Manufacturer
Altera
Datasheet

Specifications of PCI-BOARD/S25

Lead Free Status / Rohs Status
Supplier Unconfirmed
Stratix PCI Development Board Data Sheet
4
FPGA
PCI
Memory
Configuration
Clock
Control
User Settings
Table 1. Stratix PCI Development Board Components & Interfaces (Part 1 of 3)
Type
Stratix device
PCI connector
PCI level converters
DDR connector and
DDR SDRAM
Flash
MAX
controller
JTAG
Configuration done
LED (D4)
System clock
oscillator
High-speed clock
oscillator
SMA clock
System reset
pushbutton switch
User reset
pushbutton switch
Board settings dip
switch bank
User pushbutton
switches
User dip switch bank S2
Component/
®
Interface
configuration
Table 1
supports.
describes the major components on the board and the interfaces it
U2
J11
U13 through
U22
J10
U3
U1
J1, J17
D4
Installed at
J14
Installed at
J15
J16
PB3
PB1
S1
PB2, PB4
Reference
Board
Configurable Stratix device. See
The EP1S25F1020C5 device is installed on the Starter
Board. The EP1S60F1020C6 device is installed on the
Professional Board.
Universal PCI and PCI-X interface. See
page
Level converters for 5.0-V PCI compatibility.
DDR SDRAM connector (SODIMM) including pre-
installed 256-MByte PC333 DDR SDRAM memory
module.
64-Mbit AMD DL-family boot-block flash.
Factory-programmed EPM3256ATC144-7 for Stratix
device configuration.
JTAG test and control as well as ByteBlaster II
configuration interface. JTAG chain jumper.
Indicates Stratix configuration is complete.
33.333-MHz system clock.
100-MHz high-speed reference clock.
Clock input.
Reset hardware and reconfigure Stratix device.
User-defined hardware reset.
System settings and configuration selection. See
Table 4 on page
page
User configurable.
User configurable.
8.
9,
Table 8 on page
9,
Table 5 on page
Description
12, and
Table 2 on page
Table 11 on page
Altera Corporation
9,
Table 6 on
Table 3 on
8.
16.