PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 59

no-image

PCI-BOARD/S25

Manufacturer Part Number
PCI-BOARD/S25
Description
Manufacturer
Altera
Datasheet

Specifications of PCI-BOARD/S25

Lead Free Status / Rohs Status
Supplier Unconfirmed
E
D
C
B
A
NOTES:
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
1.
2.
3.
Altera Stratix Schematic Symbol Breakdown:
Board is to be powered from any ONE of the following interfaces at any one time:
Related Documents
(a)
(b)
(c)
(d)
(e)
( f)
(g)
(h)
(i)
(j)
(k)
(l)
(a)
(b) ATX Power Connector
(a)
(b)
(c)
(d)
(e)
( f)
(g)
(h)
Analog Ground
Ground
Bank1 - HSDI
Bank2 - HSDI
Bank3 - GPIO/DDR/PCI
Bank4 - GPIO/DDR/PCI
Bank5 - HSDI
Bank6 - HSDI
Bank7 - GPIO/DDR/PCI
Bank8 - GPIO/DDR/PCI
Configuration/GPIO
Clocks/GPIO
VCCINT/GND
VCCIO/GND
PCI Edge Connector
100-0216200-01
110-0216200-01
120-0216200-01
130-0216200-01
140-0216200-01
150-0216200-01
160-0216200-01
170-0216200-01
8
8
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic
Film
BOM
SAMTEC QTE-060
EDGE CONNECTOR
1x 8-BIT HIGH-SPEED PORT
VCCIO = 2.5V -or- 3.3V
10/100 MAC/PHY
RS-232 SIGNALS
VCCIO = 3.3V
BANK 5
BANK 6
7
7
DDR SDRAM DATA LANES 0, 1, 2, 3
DDR SDRAM ADDRESS, PARITY BITS
6
PCI SIGNALS
USER DIPSWITCH
6
VCCIO = 2.5V
VCCIO = 3.3V
BANK 4
BANK 7
506 Parts, 50 Library Parts, 846 Nets, 3967 Pins
Stratix Package Top View
5
5
DDR SDRAM DATA LANES 4, 5, 6, 7
DDR SDRAM ADDRESS, MASK BITS
PCI SIGNALS
FLASH ADDRESS, DATA
USER LEDS
VCCIO = 3.3V
VCCIO = 2.5V
BANK 8
BANK 3
4
4
MICTOR, LCD HEADER
PUSHBUTTONS
SANTA CRUZ DAUGHTERCARD
VCCIO = 2.5V -or- 3.3V
SAMTEC QTE-080
TOP/BOT CONNECTORS
2x 8-BIT HIGH-SPEED PORTS
REV
A
B
VCCIO = 3.3V
BANK 2
BANK 1
DATE
12/02/2002
02/12/2003
3
3
PAGES
10, 13-14,
16-18
All
Changed to Rev A, first fabricated PCB revision.
Modified J8/J9 symbols to add chamfer, Changed J13 symbol TX/RX naming, Pulled
down LAN_ADSn & LAN_LCLK, Labelled RS-232 RX/TX LEDs, Modified 2.5V
Regulator Circuit, Changed B1/B6 VCCIO select fuses to jumpers, Separated
CONF_DONEn LED signal from CONF_DONE config signal, Changed C1/C2 to
47uF.
Title
Size
Date:
PAGE
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Stratix PCI Development Board
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Document Number
Wednesday, February 12, 2003
Title, Notes, Revision History
Primary PCI
PCI Voltage Limit Switches
PCI Voltage Switch Bypass Resistors
Stratix Bank 7, 8, LEDs
DDR SDRAM SO-DIMM
DDR-SDRAM Terminations
Stratix Bank 2, 5
Stratix Bank 3, 4
Bank 1 HSDI Top/Bottom Connectors
Bank 1 Debug, Bank 6 HSDI Connector
Stratix Bank 1, 6
10/100 Ethernet Interface
Santa Cruz Card, RS-232, LCD Header
Clocking, JTAG Bypass Jumper
Power
CPLD, Flash, Board-Specific DIP Switches
Decoupling
-
-
-
-
-
-
-
2
2
DESCRIPTION
DESCRIPTION
150-0216200-01
Sheet
1
1
1
o f
18
R e v
B
E
D
C
B
A