PCI-BOARD/S25 Altera, PCI-BOARD/S25 Datasheet - Page 36

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PCI-BOARD/S25

Manufacturer Part Number
PCI-BOARD/S25
Description
Manufacturer
Altera
Datasheet

Specifications of PCI-BOARD/S25

Lead Free Status / Rohs Status
Supplier Unconfirmed
Stratix PCI Development Board Data Sheet
Figure 9. DDR SDRAM Memory Termination Connections
36
Stratix Device Banks 3 & 4
DDR SDRAM Memory
The DDR SDRAM memory module installed at J10 uses SSTL-2 signaling
and termination. A reference voltage of 1.25 V is supplied to banks 3 and
4 for SSTL-2 receiver biasing. On-board resistors provide fly-by
termination at the DDR SDRAM memory connector pins. J10 is the
SODIMM connector for the DDR SDRAM memory.
DDR SDRAM memory termination connections.
Table 29
connections.
DDR_CLKEN0
DDR_CLKEN1
DDR_CS0n
DDR_CS1n
DDR_RASn
DDR_CASn
DDR_WEn
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
Table 29. DDR SDRAM Memory & Fly-By Terminators (Part 1 of 4)
DDR SDRAM Signal
DDR SDRAM Memory Connector
shows the DDR SDRAM memory and fly-by termination
Fly-By Termination Resistors
Connector (J10)
DDR SDRAM
121
122
118
120
119
112
111
110
109
108
107
106
105
102
101
115
96
95
256-MByte DDR SDRAM Memory Module
Fly-By Terminator
RN29.13
RN29.14
RN12.16
RN12.15
RN33.11
RN33.10
RN33.15
RN33.16
RN31.10
RN31.11
RN31.12
RN31.13
RN31.14
RN31.15
RN31.16
RN33.14
RN33.9
RN31.9
Figure 9
Altera Corporation
shows the
Stratix Pin
(U2)
C14
G24
H22
H23
H20
H19
G23
G21
G20
H11
H12
H13
B14
F24
F23
F20
F19
J24