SI3018-F-FSR Silicon Laboratories Inc, SI3018-F-FSR Datasheet - Page 110

• Manufacturer Part Number: SI3018-F-FSR
• Description: Modem Chip Chipset 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-F-FSR

• Package: 16SOIC
• Main Category: Chipset
• Sub-category: Data/Voice
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Digital
• Typical Supply Current: 8.5 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Data Rate: 54.6875Kbps
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Si3050 + Si3018/19
D
Revision 1.01 to Revision 1.1
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Revision 1.1 to Revision 1.2
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Revision 1.2 to Revision 1.3
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110
OCUMENT
Added package thermal information in Table 1,
“Recommended Operating Conditions and Thermal
Information,” on page 5.
Added Note 10 to the transhybrid balance parameter
in Table 4 on page 8.
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Removed R54 and R55 from "3. Bill of Materials" on
page 18.
Changed recommended DCV setting for Japan from
01 to 10 in Table 13 on page 21.
Updated initialization procedure in "5.3. Initialization"
on page 24.
Removed incorrect description of FDT bit in "5.8.
Exception Handling" on page 26.
Updated Billing Tone and Receive Overload section.
Changed to "5.22. Receive Overload Detection" on
page 33.
Updated text and added description of hybrid
coefficient format in "5.28. Transhybrid Balance" on
page 37.
Removed references to line-side revisions C and E.
Updated "9. Ordering Guide" on page 102.
Updated package information for 20-Pin TSSOP and
16-Pin SOIC on pages 103 and 104.
Added "13. Package Outline: 16-Pin TSSOP" on
page 107.
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
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Updated Table 13, “Country Specific Register
Settings,” on page 21.
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Updated "5.3. Initialization" on page 24.
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Updated Figure 25, “Si3018/19 Signal Flow
Diagram,” on page 37.
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Updated "9. Ordering Guide" on page 102.
Updated Deep Sleep Total Supply Current from 1.0
to 1.3 mA typical
Updated package pictures
Removed all SPIM references (SPIM bit is never
Updated delay time between chip selects.
Corrected ACIM settings for Brazil.
Revised Step 6 with standard hexadecimal notation.
Corrected HPF pole.
C
HANGE
L
IST
Rev. 1.31
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Revision 1.1 to Revision 1.31
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present in any Si3050 device).
Removed SnPb package options
Minor typo corrections
The internal System-Side Revision value (REVA[3:0]
in Register 11) has been incremented by one for
Si3050 revision E.