SI3018-F-FSR Silicon Laboratories Inc, SI3018-F-FSR Datasheet - Page 38

• Manufacturer Part Number: SI3018-F-FSR
• Description: Modem Chip Chipset 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-F-FSR

• Package: 16SOIC
• Main Category: Chipset
• Sub-category: Data/Voice
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Digital
• Typical Supply Current: 8.5 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Data Rate: 54.6875Kbps
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Si3050 + Si3018/19
The PLL clock synthesizer settles quickly after powerup.
However, the settling time depends on the PCLK
frequency and it can be approximately predicted by the
following equation:
For all valid PCLK frequencies listed above, the default
line sample rate is 8 kHz. This sample rate can be
increased to 16 kHz by setting the HSSM bit
(Register 7, bit 3). Regardless of the sample rate
frequency, the serial data communication rate of the
PCM and GCI highways remains 8 kHz. When the
16 kHz sample rate is selected, additional timeslots in
the PCM or GCI highway are used to transfer the
additional data.
5.31. Communication Interface Mode
The Si3050 supports two communication interface
protocols:
38
PCLK
Selection
N
T
settle
= 64/F
PCLK
PFD
Note: Values shown are the states of the pins at the rising edge of
SCLK
Table 19. PCM or GCI Highway Mode Selection
1
0
0
RESET.
Figure 27. PLL Clock Synthesizer
SDI
X
0
1
Internal PLL
Register
DIV M
Rev. 1.31


A pin-strapping method (specifically, the state of SCLK
on power-up [reset]) is used to select between the two
communication interface protocols. Tables 18 and 19
specify how to select a communication mode, and how
the various pins are used in each mode.
When operating in PCM/SPI mode, the GCI control
register should not be written (i.e., Register 42 must
each remain set at 0000_0000 when using the PCM/
SPI highway mode). Similarly, when operating in GCI
highway mode the PCM registers should not be written
(i.e., Registers 33–37 must remain set to 0000_0000
when using the GCI highway mode).
B2 Channel used
B1 Channel used
PCM/SPI mode where data and control information
transmission/reception occurs across separate
buses (PCM highway for data, and SPI port for
control).
GCI mode where data and control information is
multiplexed and transmission/reception occurs
across the GCI highway bus.
Mode Selected
PCM Mode
GCI Mode,
GCI Mode,
VCO
2
2
16.384 MHz