SI3018-F-FSR Silicon Laboratories Inc, SI3018-F-FSR Datasheet - Page 50

• Manufacturer Part Number: SI3018-F-FSR
• Description: Modem Chip Chipset 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-F-FSR

• Package: 16SOIC
• Main Category: Chipset
• Sub-category: Data/Voice
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Digital
• Typical Supply Current: 8.5 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Data Rate: 54.6875Kbps
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Si3050 + Si3018/19
The Idle state is achieved by the MX and MR bits being
held inactive (signal is high) for two or more frames.
When a transmission is initiated by a host device, an
active state (signal is low) is present on the downstream
MX bit. This signals to the Si3050 that a transmission
has begun on the Monitor channel and the Si3050
should begin accepting data from host device. The
Si3050, after reading the data on the Monitor channel,
acknowledges the initial transmission by placing the
upstream MR bit in an active state. The data is received
and the upstream MR becomes active in the frame
immediately following the downstream MX becoming
active. The upstream MR then remains active until
either the next byte is received or an end of message is
detected. The end of message is signaled by the
downstream MX being held inactive for two or more
consecutive frames. Receipt of initial data is signaled by
the upstream MR bit’s transitioning from an inactive to
an active state. Upon receiving acknowledgement from
the Si3050 that the initial data is received, the host
device places the downstream MX bit in the inactive
state for one frame and then either transmit another
byte by placing the downstream MX bit in an active state
again, or signal an end of message by leaving the
downstream MX bit inactive for a second frame.
50
Transm itter
Receiver
MX
MX
MR
MR
1st Byte
Figure 42. Monitor Handshake Timing
1st Byte
ACK
125
2nd Byte

Rev. 1.31
s
When the host is performing a write command, the host
only manipulates the downstream MX bit, and the
Si3050 only manipulates the upstream MR bit. If a read
command is performed, the host initially manipulates
the downstream MX bit to communicate the command,
but then manipulates the downstream MR bit in
response to the Si3050 responding with the requested
data. Similarly, the Si3050 initially manipulates its
upstream MR bit to receive the read command, and
then manipulates its upstream MX bit to respond with
the requested data. If the host is transmitting data, the
Si3050 always transmits a $FF value on its Monitor data
byte. While the Si3050 is transmitting data, the host
should always transmit a $FF value on its Monitor byte.
If the Si3050 is transmitting data and detects a value
other than a $FF on the downstream Monitor byte, the
Si3050 signals an Abort.
For read and write commands, an initial address must
be specified. The Si3050 responds to a read or a write
command at this address, and then subsequently
increment this address after every register access.
2nd Byte
ACK
3rd Byte
3rd Byte
ACK