EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 144
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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6–36
High-Speed I/O Timing
Table 6–11. High-Speed I/O Timing Definitions
Cyclone IV Device Handbook, Volume 1
Transmitter channel-to-channel skew
Sampling window
Time unit interval
Receiver input skew margin
Input jitter tolerance (peak-to-peak)
Output jitter (peak-to-peak)
Note to
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Table
6–11:
Parameter
Figure 6–20
Figure 6–20. The Output Signal with Pre-Emphasis
This section discusses the timing budget, waveforms, and specifications for
source-synchronous signaling in Cyclone IV devices. Timing for source-synchronous
signaling is based on skew between the data and clock signals.
High-speed differential data transmission requires timing parameters provided by IC
vendors and requires you to consider the board skew, cable skew, and clock jitter. This
section provides information about high-speed I/O standards timing parameters in
Cyclone IV devices.
Table 6–11
defines the parameters of the timing diagram shown in
shows the differential output signal with pre-emphasis.
(1)
TCCS
SW
TUI
RSKM
Symbol
—
—
Negative channel (n)
Positive channel (p)
The timing difference between the fastest and slowest output
edges, including t
included in the TCCS measurement.
The period of time during which the data must be valid in order
for you to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
T
The TUI is the data-bit timing budget allowed for skew,
propagation delays, and data sampling window.
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is:
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Peak-to-peak output jitter from the PLL.
RSKM
SW
= T
SU
=
+ T
--------------------------------------------- -
TUI SW TCCS
hd
+ PLL jitter.
–
CO
2
variation and clock skew. The clock is
–
Chapter 6: I/O Features in Cyclone IV Devices
Description
Overshoot
Undershoot
V
OD
© December 2010 Altera Corporation
Figure
High-Speed I/O Timing
6–21.
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