EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 363

• Manufacturer Part Number: EP4CGX15BF14C8N
• Description: IC CYCLONE IV FPGA 15K 169FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX15BF14C8N

• Number Of Logic Elements/cells: 14400
• Number Of Labs/clbs: 900
• Total Ram Bits: 540000
• Number Of I /o: 72
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 169-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1475

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–28. PIPE Interface Ports in ALTGX Megafunction for Cyclone IV GX
© December 2010 Altera Corporation
fixedclk
tx_detectrx
loop
tx_forcedisp
compliance
pipe8b10binvpo
larity
powerdn
pipedatavalid
pipephydone
status
pipeelecidle
pipestatus
Port Name
Output
Output N/A
Output Asynchronous signal
Output Asynchronous signal
Output N/A
Input/
Input
Input
Input
Input
Input
Clock signal
Asynchronous signal
Asynchronous signal
Asynchronous signal
Asynchronous signal
Clock Domain
Invert the polarity of every bit of the 10-bit input to the 8B/10B decoder
125-MHz clock for receiver detect and offset cancellation only in PIPE
mode.
Receiver detect or reverse parallel loopback control.
■
■
Force the 8B/10B encoder to encode with negative running disparity.
■
PIPE power state control.
■
Valid data and control on the rx_dataout and rx_ctrldetect ports
indicator.
PHY function completion indicator.
■
Electrical idle detected or inferred at the receiver indicator.
■
■
PIPE receiver status port.
■
A high level in the P1 power state and tx_forceelecidle signal
asserted begins the receiver detection operation to determine if there is
a valid receiver downstream. This signal must be deasserted when the
pipephydonestatus signal indicates receiver detect completion.
A high level in the P0 power state with the tx_forceelecidle
signal deasserted dynamically configures the channel to support
reverse parallel loopback mode.
Assert only when transmitting the first byte of the PIPE-compliance
pattern to force the 8B/10B encoder with a negative running disparity.
Signal is 2 bits wide and is encoded as follows:




Asserted for one clock cycle to communicate completion of several PHY
functions, such as power state transition and receiver detection.
When electrical idle inference is used, this signal is driven high when it
infers an electrical idle condition
When electrical idle inference is not used, the rx_signaldetect
signal is inverted and driven on this port.
Signal is 3 bits wide and is encoded as follows:








2'b00: P0 (Normal operation)
2'b01: P0s (Low recovery time latency, low power state)
2'b10: P1 (Longer recovery time latency, lower power state)
2'b11: P2 (Lowest power state)
3'b000: Received data OK
3'b001: one SKP symbol added
3'b010: one SKP symbol removed
3'b011: Receiver detected
3'b100: 8B/10B decoder error
3'b101: Elastic buffer overflow
3'b110: Elastic buffer underflow
3'b111: Received disparity error
(Note 1)
(Part 1 of 2)
Cyclone IV Device Handbook, Volume 2
Description
1–83