EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 473
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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Chapter 1: Cyclone IV Device Datasheet
Glossary
Table 1–46. Glossary (Part 2 of 5)
© December 2010 Altera Corporation
Letter
Q
R
P
PLL Block
R
Receiver Input
Waveform
Receiver input
skew margin
(RSKM)
L
Term
—
The following highlights the PLL specification parameters:
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver input waveform for LVDS and LVPECL differential standards:
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
Core Clock
Key
CLK
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Reconfigurable in User Mode
V
CM
V
Switchover
ID
f
IN
N
V
ID
f
INPFD
Definitions
PFD
—
M
CP
Phase tap
LF
Cyclone IV Device Handbook, Volume 3
V
ID
VCO
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
f
p - n
VCO
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
IH
IL
GCLK
1–39
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