ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 105

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ECON—Flash/EE Memory Control SFR
Programming flash memory is done through the Flash Control
SFR (ECON, 0xB9). This SFR allows the user to read, write, erase,
or verify the 16 kB of flash memory. As a method of security, a
key must be written to the FLSHKY register to initiate any user
access to the flash memory. Upon completion of the flash memory
operation, the FLSHKY register is reset so that it must be written
to prior to another flash memory operation. Requiring the key
to be set before an access to the flash memory decreases the
likelihood of user code or data being overwritten by a program
inappropriately modified during its execution.
Table 92. Flash Control SFR (ECON, 0xB9)
Bit
7 to 0
Table 93. Flash Key SFR (FLSHKY, 0xBA)
Bit
7 to 0
Table 94. Flash Protection Key SFR (PROTKY, 0xBB)
Bit
7 to 0
Table 95. Flash Data SFR (EDATA, 0xBC)
Bit
7 to 0
Table 96. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD)
Bit
7 to 0
Table 97. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE)
Bit
7 to 0
Mnemonic
PROTB1
Mnemonic
FLSHKY
Mnemonic
PROTKY
Mnemonic
EDATA
Mnemonic
PROTB0
Mnemonic
ECON
Default
0xFF
Value
1
2
3
4
5
8
Default
0xFF
Default
0xFF
Default
0
Default
0xFF
Description
This SFR is used to write the write/erase protection bits for Page 8 to Page15 of the flash memory
(see the Protecting the Flash Memory section). Clearing the bits enables the protection.
PROTB1.7
Page 15
Description
This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory
(see the Protecting the Flash Memory section). Clearing the bits enables the protection.
PROTB0.7
Page 7
Description
Write Byte. The value in EDATA is written to the flash memory at the page address given by EADRH and
EADRL. Note that the byte being addressed must be pre-erased.
Erase Page. A 512-byte page of flash memory address is erased. The page is selected by the address in
EADRH/EADRL. Any address in the page can be written to EADRH/EADRL to select it for erasure.
Erase All. All 16 kB of the flash memory are erased. Note that this command is used during serial and
parallel download modes but should not be executed by user code.
Read Byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA.
Erase Page and Write Byte. The page that holds the byte addressed by EADRH/EADRL is erased. Data in
EDATA is then written to the byte of flash memory addressed by EADRH/EADRL.
Protect Code (see the Protecting the Flash Memory section).
Description
The content of this SFR is compared to the flash key, 0x3B. If the two values match, the next ECON
operation is allowed (see the Protecting the Flash Memory section).
Description
The content of this SFR is compared to the flash memory location at Address 0x3FFA. If the two values
match, the update of the write/erase and read protection set up is allowed (see the Protecting the Flash
Memory section).
If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. This SFR is
also used to write the protection key in the flash. This is done by writing the desired value in PROTKY
and by writing 0x08 in the ECON SFR. This operation can only be done once.
Description
Flash Pointer Data.
PROTB1.6
Page 14
PROTB0.6
Page 6
Rev. A | Page 105 of 144
PROTB1.5
Page 13
PROTB0.5
Page 5
The program counter (PC) is held on the instruction where the
ECON register is written to until the flash memory controller is
done performing the requested operation. Then, the PC
increments to continue with the next instruction.
Any interrupt requests that occur while the flash controller is
performing an operation are not handled until the flash operation
is complete. All peripherals, such as timers and counters, continue
to operate as configured throughout the flash memory access.
PROTB1.4
Page 12
PROTB0.4
Page 4
ADE7566/ADE7569/ADE7166/ADE7169
PROTB1.3
Page 11
PROTB0.3
Page 3
PROTB1.2
Page 10
PROTB0.2
Page 2
PROTB1.1
Page 9
PROTB0.1
Page 1
PROTB1.0
Page 8
PROTB0.0
Page 0