ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 30

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7566/ADE7569/ADE7166/ADE7169 can be
configured to generate a PSM interrupt when the source of
V
Setting the EBSO bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC) enables this event to generate a
PSM interrupt (see Table 20).
The ADE7566/ADE7569/ADE7166/ADE7169 can also be
configured to generate an interrupt when the source of V
changes from V
has been restored. Setting the EPSR bit in the Power Management
Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate
a PSM interrupt.
The flags in the IPSME SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the
source of V
and cleared when V
V
The ADE7566/ADE7569/ADE7166/ADE7169 can be
configured to generate a PSM interrupt when V
magnitude by more than a configurable threshold. This threshold
is set in the Temperature and Supply Delta SFR (DIFFPROG,
0xF3), which is described in Table 49. See the External Voltage
Measurement section for more information. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The V
measurements take place in the background at intervals to check
the change in V
the Start ADC Measurement SFR (ADCGO, 0xD8) described in
Table 50. The FVDCIN flag indicates when a V
is ready. See the External Voltage Measurement section for
details on how V
SWOUT
DCIN
ADC PSM Interrupt
DCIN
changes from V
voltage is measured using a dedicated ADC. These
SWOUT
DCIN
BAT
. The bit is set when V
DCIN
. Conversions can also be initiated by writing to
to V
SWOUT
is measured.
DD
DD
, indicating that the V
is connected to V
to V
BAT
, indicating battery switchover.
SWOUT
BAT
is connected to V
.
DCIN
DCIN
DD
power supply
measurement
changes
SWOUT
Rev. A | Page 30 of 144
DD
V
The V
measurements take place in the background at intervals to
check the change in V
level is lower than the threshold set in the Battery Detection
Threshold SFR (BATVTH, 0xFA), described in Table 51, or
when a new measurement is ready in the Battery ADC Value
SFR (BATADC, 0xDF), described in Table 53. See the Battery
Measurement section for more information. Setting the EBAT
bit in the Power Management Interrupt Enable SFR (IPSME,
0xEC) enables this event to generate a PSM interrupt.
V
The V
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set
when the V
EVDCIN bit in the IPSME SFR enables this event to generate a
PSM interrupt. This event, which is associated with the SAG
monitoring, can be used to detect a power supply (V
compromised and to trigger further actions prior to deciding a
switch of V
SAG Monitor PSM Interrupt
The ADE7566/ADE7569/ADE7166/ADE7169 energy
measurement DSP monitors the ac voltage input at the V
V
for a line voltage SAG event. The FSAG bit in the Power
Management Interrupt Flag SFR (IPSMF, 0xF8) is set if the line
voltage stays below the level set in the SAGLVL register for the
number of line cycles set in the SAGCYC register. See the Line
Voltage SAG Detection section for more information. Setting
the ESAG bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
BAT
DCIN
N
input pins. The SAGLVL register is used to set the threshold
Monitor PSM Interrupt
Monitor PSM Interrupt
BAT
DCIN
voltage is measured using a dedicated ADC. These
voltage is monitored by a comparator. The FVDCIN
DD
DCIN
to V
input level is lower than 1.2 V. Setting the
BAT
.
BAT
. The FBAT bit is set when the battery
DD
) being
P
and