ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 89

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPT SYSTEM
The unique power management architecture of the ADE7566/
ADE7569/ADE7166/ADE7169 includes an operating mode
(PSM2) where the 8052 MCU core is shut down. Events can be
configured to wake the 8052 MCU core from the PSM2
operating mode. A distinction is drawn here between events
that can trigger the wake-up of the 8052 MCU core and events
that can trigger an interrupt when the MCU core is active.
Events that can wake the core are referred to as wake-up events,
whereas events that can interrupt the program flow when the
MCU is active are called interrupts. See the 3.3 V Peripherals
and Wake-Up Events section to learn more about events that
can wake the 8052 core from PSM2.
The ADE7566/ADE7569/ADE7166/ADE7169 provide 12
interrupt sources with three priority levels. The power
management interrupt is at the highest priority level. The other
two priority levels are configurable through the Interrupt
Priority SFR (IP, 0xB8) and Interrupt Enable and Priority 2 SFR
(IEIP2, 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
Table 67. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Table 68. Interrupt Enable SFR (IE, 0xA8)
Bit
7
6
5
4
3
2
1
0
Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Address
0xA8
0xB8
0xA9
0xC0
Figure 86. Standard 8052 Interrupt Priority Levels
Mnemonic
EA
ETEMP
ET2
ES
ET1
EX1
ET0
EX0
HIGH
LOW
Default
0x00
0x00
0xA0
0x10
PRIORITY 1
PRIORITY 0
Description
Enables All Interrupt Sources. Set by the user. Cleared by the user to disable all interrupt sources.
Enables the Temperature ADC Interrupt. Set by the user.
Enables the Timer 2 Interrupt. Set by the user.
Enables the UART Serial Port Interrupt. Set by the user.
Enables the Timer 1 Interrupt. Set by the user.
Enables the External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 Interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
Yes
No
Yes
Bit Addressable
Yes
Description
Interrupt Enable (see Table 68).
Interrupt Priority (see Table 69).
Interrupt Enable and Priority 2 (see Table 70).
Watchdog Timer (see
0xC0) section).
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occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7566/ADE7569/ADE7166/ADE7169 possess advanced
power supply monitoring features. To ensure a fast response to
time-critical power supply issues, such as a loss of line power,
the power supply monitoring interrupt should be able to
interrupt any interrupt service routine. To enable the user to have
full use of the standard 8052 interrupt priority levels, an additional
priority level is added for the power supply management (PSM)
interrupt. The PSM interrupt is the only interrupt at this highest
interrupt priority level.
See the Power Supply Monitor Interrupt (PSM) section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system is carried
out through four interrupt-related SFRs discussed in this section.
Table 75 and the
ADE7566/ADE7569/ADE7166/ADE7169
Writing to the Watchdog Timer SFR (WDCON,
Figure 87. Interrupt Architecture
HIGH
LOW
PRIORITY 1
PRIORITY 0
PSM