ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 97

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 79. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit
7
6
5 to 0
Table 80. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5]
0
1
Table 81. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit
7
6
5 to 2
1
0
Table 82. LCD Clock SFR (LCDCLK, 0x96)
Bit
7 to 6
5 to 4
3 to 0
Mnemonic
Reserved
EXTRES
BIASLVL[5:0]
Mnemonic
Reserved
INV_LVL
Reserved
UPDATEOVER
REFRESH
Mnemonic
BLKMOD[1:0]
BLKFREQ[1:0]
FD[3:0]
V
V
V
A
REF
REF
(V)
×
×
⎛
⎜
⎝
BLVL
1
+
31
BLVL
Default
0
0
0
Default
0
0
0
0
0
Default
0
0
0
[
4:0
31
]
[
4:0
]
⎞
⎟
⎠
Description
Reserved.
External Resistor Ladder Selection Bit.
EXTRES
0
1
Bias Level Selection Bits. See Table 80.
Description
This bit should be kept cleared for proper operation.
Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
These bits should be kept cleared for proper operation.
Update Finished Flag Bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
Refresh LCD Data Memory Bit. This bit should be set by the user. When set, the LCD driver does not
use the data in the LCD data registers to update the display. The LCD data registers can be updated
by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display
at the next frame.
Description
Blink Mode Clock Source Configuration Bits.
BLKMOD[1:0]
00
01
10
11
Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11.
BLKFREQ[1:0]
00
01
10
11
LCD Frame Rate Selection Bits. See Table 83 and Table 84.
V
V
V
B
B
B
= V
= V
Result
External resistor ladder is disabled. Charge pump is enabled.
External resistor ladder is enabled. Charge pump is disabled.
Rev. A | Page 97 of 144
A
A
Result
The blink rate is controlled by software. The display is off.
The blink rate is controlled by software. The display is on.
The blink rate is 2 Hz.
The blink rate is set by BLKFREQ[1:0].
Result (Blink Rate)
1 Hz
1/2 Hz
1/3 Hz
1/4 Hz
1/2 Bias
V
V
V
ADE7566/ADE7569/ADE7166/ADE7169
C
C
C
= 2 × V
= 2 × V
A
A
V
V
V
B
B
B
= 2 × V
= 2 × V
A
A
1/3 Bias
V
V
V
C
C
C
= 3 × V
= 3 × V
A
A