ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 71

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENERGY-TO-FREQUENCY CONVERSION
The ADE7566/ADE7569/ADE7166/ADE7169 also provide two
energy-to-frequency conversions for calibration purposes. After
initial calibration at manufacturing, the manufacturer or end
customer often verify the energy meter calibration. One
convenient way to do this is for the manufacturer to provide an
output frequency that is proportional to the active power,
reactive power, apparent power, or I
conditions. This output frequency can provide a simple, single-
wire, optically isolated interface to external calibration equipment.
Figure 78 illustrates the energy-to-frequency conversion in the
ADE7566/ADE7569/ADE7166/ADE7169.
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when CFxNUM/CFxDEN number of
pulses are generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active
power, reactive power, apparent power, or I
CFxSEL bits in the MODE2 register (0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting Bit DISCF1 and Bit DISCF2 in the MODE1 register
(0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, 0xDD), CF1 and CF2. If the CF1 and CF2 enable
bits in the Interrupt Enable 2 SFR (MIRQENM, 0xDA) are set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CF1 or CF2 status bits are cleared (see the
Energy Measurement Interrupts section).
I
VA
rms
VARMSCFCON
MODE 2 REGISTER 0x0C
WATT
* AVAILABLE ONLY IN THE ADE7569 AND ADE7169
VAR *
Figure 78. Energy-to-Frequency Conversion
CFxSEL[1:0]
DFC
rms
under steady load
CFxNUM
CFxDEN
÷
rms
, depending on the
CFx PULSE
OUTPUT
Rev. A | Page 71 of 144
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 Register (0x0C. Setting the CFxSEL bits to 0b00,
0b01, or 0b1x configures the DFC to create a pulse output
proportional to active power, to reactive power (not available in
the ADE7566 and ADE7166), or to apparent power or I
respectively.
The selection between I
VARMSCFCON bit in the MODE2 register (0x0C). With this
selection, CF2 cannot be proportional to apparent power if CF1
is proportional to I
apparent power if CF2 is proportional to I
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should preferably be
connected to an LED, as shown in Figure 79.
The maximum output frequency with ac input signals at
full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is
approximately 21.1 kHz.
The ADE7566/ADE7569/ADE7166/ADE7169 incorporate two
registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set
the CFx frequency. These are unsigned 16-bit registers that can
be used to adjust the CFx frequency to a wide range of values.
These frequency scaling registers are 16-bit registers that can
scale the output frequency by 1/2
If 0 is written to any of these registers, 1 is applied to the
register. The ratio CFxNUM/CFxDEN should be less than 1 to
ensure proper operation. If the ratio of the CFxNUM/CFxDEN
registers is greater than 1, the register values are adjusted to a
ratio of 1. For example, if the output frequency is 1.562 kHz
while the content of CFxDEN is 0 (0x000), the output frequency
can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.
ADE7566/ADE7569/ADE7166/ADE7169
rms
Figure 79. CF Pulse Output
, and CF1 cannot be proportional to
rms
CF
and apparent power is done by the
V
DD
16
to 1 with a step of 1/2
rms
.
rms
16
,
.