CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 18

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

load. Therefore, the crystal must have a required load capacitance of about 15–18 pF. A ceramic resonator does not allow the
microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with
these parts.
An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.
7.0
The CY7C66x13 supports two resets: POR and a Watchdog Reset (WDR). Each of these resets causes:
The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 15.0. Bits 4 and 6
are used to record the occurrence of POR and WDR, respectively. Firmware can interrogate these bits to determine the cause
of a reset.
Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler should configure the hardware before the “main” loop of code. Attempting to execute a RET or RETI in the firmware
reset handler causes unpredictable execution results.
7.1
When V
semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator and all other blocks
of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid V
the internal PLL has time to stabilize before full operation begins. When the V
oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is not interruptible,
and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream
port. The 95 ms provides time for V
If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command.
The POR signal is asserted whenever V
again. Behavior is the same as described above.
7.2
The WDR occurs when the internal WDT rolls over. Writing any value to the write-only Watchdog Restart Register at address
0x26 clears the timer. The timer rolls over and WDR occurs if it is not cleared within t
6 of the Processor Status and Control Register is set to record this event (the register contents are set to 010X0001 by the WDR).
A WDT Reset lasts for 2 ms, after which the microcontroller begins execution at ROM address 0x0000.
The USB transmitter is disabled by a WDR because the USB Device Address Registers are cleared (see Section 19.1).
Otherwise, the USB Controller would respond to all address 0 transactions.
Document #: 38-08024 Rev. *A
• all registers to be restored to their default states
• the USB device addresses to be set to 0
• all interrupts to be disabled
• the PSP and DSP to be set to memory address 0x00.
CC
Power-on Reset
Watchdog Reset
Reset
is first applied to the chip, the POR signal is asserted and the CY7C66x13 enters a “semi-suspend” state. During the
Last write to
WDT
Register
CC
to stabilize at a valid operating voltage before the chip executes code.
CC
drops below approximately 2.5V, and remains asserted until V
t
WATCH
Figure 7-1. Watchdog Reset
No write to WDT
register, so WDR
goes HIGH
2 ms
Execution begins at
Reset Vector 0x0000
CC
has risen above approximately 2.5V, and the
WATCH
(8 ms minimum) of the last clear. Bit
CC
level is reached and that
CC
rises above this level
CY7C66013
CY7C66113
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