CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 35

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

Bit [0..6] : Port x Connect Status (where x = 1..7)
Bit 7 : Reserved.
The Hub Ports Connect Status register is cleared to zero by reset or USB bus reset, then set to match the hardware configuration
by the hub repeater hardware. The Reserved bit [7] should always read as ‘0’ to indicate no connection.
Bit [0..6] : Port x Speed (where x = 1..7)
Bit 7 : Reserved.
The Hub Ports Speed register is cleared to zero by reset or bus reset. This must be set by the firmware on issuing a port reset.
The Reserved bit [7] should always read as ‘0.’
18.2
After a USB device connection has been detected, firmware must update status change bits in the hub status change data
structure that is polled periodically by the USB host. The host responds by sending a packet that instructs the hub to reset and
enable the downstream port. Firmware then sets the bit in the Hub Ports Enable register, Figure 18-3, for the downstream port.
The hub repeater hardware responds to an enable bit in the Hub Ports Enable register by enabling the downstream port, so that
USB traffic can flow to and from that port.
If a port is marked enabled and is not suspended, it receives all USB traffic from the upstream port, and USB traffic from the
downstream port is passed to the upstream port (unless babble is detected). Low-speed ports do not receive full-speed traffic
from the upstream port.
When firmware writes to the Hub Ports Enable register to enable a port, the port is not enabled until the end of any packet currently
being transmitted. If there is no USB traffic, the port is enabled immediately.
When a USB device disconnection has been detected, firmware must update status bits in the hub change status data structure
that is polled periodically by the USB host. In suspend, a connect or disconnect event generates an interrupt (if the hub interrupt
is enabled) even if the port is disabled.
Hub Ports Enable Register
Bit [0..6] : Port x Enable (where x = 1..7)
Bit 7 : Reserved.
The Hub Ports Enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition.
A port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. Babble is
defined as:
18.3
Data transfer on hub downstream ports is controlled according to the bit settings of the Hub Downstream Ports Control Register
(Figure 18-4). Each downstream port is controlled by two bits, as defined in Table 18-1 below. The Hub Downstream Ports Control
Document #: 38-08024 Rev. *A
Hub Ports Speed
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
• Any non-idle downstream traffic on an enabled downstream port at EOF2
• Any downstream port with upstream connectivity established at EOF2 (i.e., no EOP received by EOF2).
When set to 1, Port x is connected; When set to 0, Port x is disconnected.
Set to 0.
Set to 1 if the device plugged in to Port x is Low Speed; Set to 0 if the device plugged in to Port x is Full Speed.
Set to 0.
Set to 1 if Port x is enabled; Set to 0 if Port x is disabled.
Set to 0.
Enabling/Disabling a USB Device
Hub Downstream Ports Status and Control
7
Reserved
R/W
0
7
Reserved
R/W
0
6
Port 7 Speed
R/W
0
6
Port 7 Enable
R/W
0
5
Port 6 Speed
R/W
0
5
Port 6 Enable
R/W
0
Figure 18-3. Hub Ports Enable Register
Figure 18-2. Hub Ports Speed
4
Port 5 Speed
R/W
0
4
Port 5 Enable
R/W
0
3
Port 4 Speed
R/W
0
3
Port 4 Enable
R/W
0
2
Port 3 Speed
R/W
0
2
Port 3 Enable
R/W
0
1
Port 2 Speed
R/W
0
1
Port 2 Enable
R/W
0
CY7C66013
CY7C66113
ADDRESS 0x4A
ADDRESS 0x49
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0
Port 1 Speed
R/W
0
0
Port 1 Enable
R/W
0