CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 46

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend)
Document #: 38-08024 Rev. *A
See
Table 16-1
See
Table 16-1
See
Table 16-1
DISABLED
0 0
Nak In/Out
0 0
0 0
Ignore In/Out
0 1
0 1
Stall In/Out
0 0
0 0
Normal Out/premature status In
1 0
1 0
1 0
1 0
NAK Out/premature status In
1 0
1 0
1 0
1 0
Status In/extra Out
0 1
0 1
0 1
0 1
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
Mode Bits
Mode Bits
Mode Bits
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete. This represents about a 1- s window in which the CPU is locked
from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that
the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of
the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to
make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This
read will of course unlock the register. So care must be taken not to overwrite the register elsewhere.
Properties of Incoming Packet
Properties of Incoming Packet
Properties of Incoming Packet
Properties of Incoming Packet
0 0
0 1
0 1
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
Setup <= 10 data
Setup > 10
Setup x
x
Out
In
Out
In
Out
In
Out
Out
Out
In
Out
Out
Out
In
Out
Out
Out
In
token count buffer
token count buffer
token count buffer
x
x
x
x
x
x
x
<= 10 data
> 10
x
x
<= 10 UC
> 10
x
x
<= 10 UC
> 10
x
x
junk
junk
UC
UC
UC
UC
UC
UC
UC
junk
junk
UC
UC
UC
UC
UC
UC
UC
x
x
x
x
x
valid
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
x
dval
dval
dval
updates 1
updates updates updates 1
updates 0
UC
UC
UC
UC
UC
UC
UC
updates 1
updates updates updates UC
updates 0
UC
UC
UC
UC
UC
UC
UC
UC
UC
SETUP (if accepting SETUPs)
DTOG
DTOG
DTOG
CONTROL WRITE
CONTROL READ
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
Changes made by SIE to Internal Registers and Mode Bits
Changes made by SIE to Internal Registers and Mode Bits
Changes made by SIE to Internal Registers and Mode Bits
DVAL COUNT Setup In Out ACK Mode Bits Response Intr
DVAL COUNT Setup In Out ACK Mode Bits Response Intr
DVAL COUNT Setup In Out ACK Mode Bits Response Intr
updates 1
updates 1
UC
UC
UC
UC
UC
UC
UC
updates UC
updates UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC UC 1
UC UC UC
UC UC UC
UC 1
UC 1
UC 1
UC UC UC
UC UC UC
UC UC UC
UC UC UC
UC 1
1
UC UC UC
UC 1
1
1
UC 1
UC UC UC
1
UC 1
UC UC UC
1
UC UC
UC UC
UC 1
UC 1
UC 1
UC
UC
1
UC
UC
UC
UC
0 0 0 1 ACK
1 0 1 0 ACK
NoChange ignore
NoChange ignore
NoChange ignore
NoChange ignore
NoChange ignore
NoChange ignore
NoChange ignore
NoChange NAK
NoChange NAK
NoChange ignore
NoChange ignore
NoChange Stall
NoChange Stall
NoChange TX 0
NoChange NAK
NoChange ignore
NoChange TX 0
0 0 1 1 Stall
NoChange ignore
NoChange TX 0
CY7C66013
CY7C66113
Page 46 of 58
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no
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