CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 48

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) (continued)
21.0
Document #: 38-08024 Rev. *A
1 1
1 1
NAK In/erroneous Out
1 1
1 1
Isochronous endpoint (In)
0 1
0 1
Notes:
5.
6.
7.
B: Read and Write.
W: Write.
R: Read.
0x00 Port 0 Data
0x01 Port 1 Data
0x02 Port 2 Data
0x03 Port 3 Data
0x04 Port 0 Interrupt
0x05 Port 1 Interrupt
0x06 Port 2 Interrupt
0x07 Port 3 Interrupt
0x08 GPIO Configu-
0x09 HAPI/I
0x10 USB Device
Addr
ess
0 1
0 1
0 0
0 0
1 1
1 1
Register Summary
Enable
Enable
Enable
Enable
ration
ration
Address A
Register Name
Out
In
Out
In
Out
In
2
C Configu-
x
x
x
x
x
x
UC
UC
UC
UC
UC
UC
P0.7
P1.7
P2.7
P3.7
P0.7 Intr
Enable
P1.7 Intr
Enable
P2.7 Intr
Enable
Reserve
d
Port 3
Config
Bit 1
I
Position
Device
Address
A Enable
2
C
Bit 7
x
x
x
x
x
x
P0.6
P1.6
P2.6
P3.6
P0.6 Intr
Enable
P1.6 Intr
Enable
P2.6 Intr
Enable
Reserve
d
Port 3
Config
Bit 0
Reserve
d
Device
Address
A
Bit 6
Bit 6
UC
UC
UC
UC
UC
UC
P0.5
P1.5
P2.5
P3.5
P0.5 Intr
Enable
P1.5 Intr
Enable
P2.5 Intr
Enable
Reserve
d
Port 2
Config
Bit 1
Reserve
d
Device
Address
A
Bit 5
Bit 5
UC
UC
UC
UC
UC
UC
P0.4
P1.4
P2.4
P3.4
P0.4 Intr
Enable
P1.4 Intr
Enable
P2.4 Intr
Enable
Reserve
d
Port 2
Config
Bit 0
Reserve
d
Device
Address
A
Bit 4
Bit 4
UC
UC
UC
UC
UC
UC
P0.3
P1.3
P2.3
P3.3
P0.3 Intr
Enable
Reserve
d
P2.3 Intr
Enable
Reserve
d
Port 1
Config
Bit 1
Reserve
d
Device
Address
A
Bit 3
Bit 3
UC
UC
UC
UC
UC
UC
P0.2
P1.2
P2.2
P3.2
P0.2 Intr
Enable
P1.2 Intr
Enable
Reserve
d
Reserve
d
Port 1
Config
Bit 0
Reserve
d
Device
Address
A
Bit 2
Bit 2
1
1
UC UC UC
UC UC UC
1
UC UC UC
UC 1
UC UC
UC UC
P0.1
P1.1
P2.1
P3.1
P0.1 Intr
Enable
P1.1 Intr
Enable
Reserve
d
P3.1 Intr
Enable
Port 0
Config
Bit 1
I
Width
Device
Address
A
Bit 1
2
C Port
Bit 1
1 1 0 0 ACK (back) yes
NoChange TX
NoChange stall
NoChange ignore
NoChange NAK
NoChange ignore
P0.0
P1.0
P2.0
P3.0
P0.0 Intr
Enable
P1.0 Intr
Enable
Reserve
d
P3.0 Intr
Enable
Port 0
Config
Bit 0
Reserve
d
Device
Address
A
Bit 0
Bit 0
Read/Write
/Both
bbbbbbbb 1111111
bbbbbbbb 1111111
bbbbbbbb 1111111
bbbbbbbb 1111111
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
bbbbbbbb 000000
bbbbbbbb 000000
bbbbbbbb 000000
CY7C66013
CY7C66113
(STALL
0)
(STALL
1)
[5, 6, 7]
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[4]
[4]
=
=
Default/
1
1
1
1
000000
00
000000
00
000000
00
000000
00
00
00
00
Reset
no
no
yes
no
yes