CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 38

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

Bit [0..6] : Resume x (where x = 1..7)
Bit 7 : Reserved.
Resume from a selectively suspended port, with the hub not in suspend, typically involves these actions:
Resume when the hub is suspended typically involves these actions:
Firmware can choose to clear the Device Remote Wake-up bit (if set) to implement firmware timed states for port changes. All
allowed port changes wake the part. Then, the part can use internal timing to determine whether to take action or return to
suspend. If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events.
18.5
USB status and control is regulated by the USB Status and Control Register, as shown in Figure 18-11. All bits in the register are
cleared during reset.
Bits[2..0] : Control Action
Document #: 38-08024 Rev. *A
USB Status and Control
1. Hardware detects the Resume, drives a K to the port, and generates the hub interrupt. The corresponding bit in the Resume
2. Firmware responds to hub interrupt, and reads register 0x4E to determine the source of the Resume.
3. Firmware begins driving K on the port for 10 ms or more through register 0x4B.
4. Firmware clears the Selective Suspend bit for the port (0x4D), which clears the Resume bit (0x4E). This ends the hardware-driv-
5. Firmware drives a timed SE0 on the port for two low-speed bit times as appropriate. Note: Firmware must disable interrupts
6. Firmware drives a J on the port for one low-speed bit time, then it idles the port.
7. Firmware re-enables the port.
1. Hardware detects the Resume, drives a K on the upstream (which is then reflected to all downstream enabled ports), and
2. The part comes out of suspend and the clocks start.
3. Once the clocks are stable, firmware execution resumes. An internal counter ensures that this takes at least 1 ms. Firmware
4. The Resume ends when the host stops sending K from upstream. Firmware should check for changes to the Enable and
Bit #
Bit Name
Read/Write
Reset
Status Register (0x4E) reads ‘1’ in this case.
en Resume, but the firmware-driven Resume continues. To prevent traffic being fed by the hub repeater to the port during or
just after the Resume, firmware should disable this port.
during this SE0 so the SE0 pulse isn’t inadvertently lengthened and appears as a bus reset to the downstream device.
generates the hub interrupt.
should check for Resume from any selectively suspended ports. If found, the Selective Suspend bit for the port should be
cleared; no other action is necessary.
Connect Registers. If a port has become disabled but is still connected, an SE0 has been detected on the port. The port should
be treated as having been reset, and should be reported to the host as newly connected.
When set to 1 Port x requesting to be resumed (set by hardware); default state is 0;
Set to 0.
Set to control action as per Table 18-2.The three control bits allow the upstream port to be driven manually by firmware.
For normal USB operation, all of these bits must be cleared. Table 18-2 shows how the control bits affect the upstream port.
USB Upstream Port Status and Control
7
Endpoint Size
R/W
0
6
Endpoint Mode D+ Upstream
R/W
0
5
R
0
Figure 18-11. USB Status and Control Register
4
D– Upstream
R
0
3
Bus Activity
R/W
0
2
Control Action
Bit 2
R/W
0
1
Control Action
Bit 1
R/W
0
CY7C66013
CY7C66113
ADDRESS 0x1F
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0
Control Action
Bit 0
R/W
0