CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet - Page 41

• Manufacturer Part Number: CY7C66113-PVC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113-PVC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1330

Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the mode registers of other endpoints.
Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies
that the contents have changed as desired, and that the SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 19-1 for the appropriate endpoint zero
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 18-1.
Additional information on the mode bits can be found in Table 20-2 and Table 20-1.
Note: The SIE offers an “Ack out - Status in” mode and not an “Ack out - Nak in” mode. Therefore, if following the status stage
of a Control Write transfer a USB host were to immediately start the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
19.4
The format of the non-control endpoint mode registers is shown in Figure 19-3.
Bits[3..0] : Mode
Bit 4 : ACK
Bits[6..5] : Reserved
Bit 7 : STALL
19.5
There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 19-4.
USB Endpoint Counter
Bits[5..0] : Byte Count
Document #: 38-08024 Rev. *A
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
USB Non-Control Device Endpoint Mode
These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in
Table 18-1.
This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
Must be written zero during register writes.
These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with
the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or
SETUP transactions, the count is updated by hardware to the number of data bytes received, plus two for the CRC bytes.
Valid values are 2 to 34, inclusive.
If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the
mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.
USB Non-Control Endpoint Mode Registers
USB Endpoint Counter Registers
7
STALL
R/W
0
7
Data 0/1 Toggle Data Valid
R/W
0
6
Reserved
R/W
0
6
R/W
0
Figure 19-3. USB Non-Control Device Endpoint Mode Registers
5
Reserved
R/W
0
5
Byte Count Bit
5
R/W
0
Figure 19-4. USB Endpoint Counter Registers
4
ACK
R/W
0
4
Byte Count Bit
4
R/W
0
3
Mode Bit 3
R/W
0
3
Byte Count Bit
3
R/W
0
2
Mode Bit 2
R/W
0
2
Byte Count Bit
2
R/W
0
ADDRESSES
1
Mode Bit 1
R/W
0
1
Byte Count Bit
1
R/W
0
ADDRESSES 0x14, 0x16, 0x44
0x11, 0x13, 0x15, 0x41, 0x43
CY7C66013
CY7C66113
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0
Mode Bit 0
R/W
0
0
Byte Count Bit
0
R/W
0