MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 15

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4
4.1
Table 6
4.2
Table 7
MPC8555E.
Freescale Semiconductor
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are ±1% of the input frequency with a maximum of 60 kHz of modulation regardless
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise time
EC_GTX_CLK125 fall time
EC_GTX_CLK125 duty cycle
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
of the input frequency.
Clock Timing
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the system clock (SYSCLK) AC timing specifications for the MPC8555E.
provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
System Clock Timing
TSEC Gigabit Reference Clock Timing
Parameter/Condition
Parameter/Condition
Table 7. EC_GTX_CLK125 AC Timing Specifications
RGMII, RTBI
Table 6. SYSCLK AC Timing Specifications
GMII, TBI
t
t
KHK
G125H
Symbol
Symbol
f
t
t
SYSCLK
SYSCLK
t
KH
t
f
t
G125R
G125F
/t
G125
G125
—
SYSCLK
, t
/t
KL
G125
Min
Min
6.0
0.6
45
47
—
40
—
—
—
—
—
Typical
Typical
125
1.0
—
—
—
—
—
—
—
8
+/- 150
Max
Max
166
1.0
1.0
1.2
60
—
—
55
53
—
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ps
%
%
Clock Timing
Notes
Notes
1, 2
4, 5
—
—
—
1
1
1
2
3
15