MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 67

IC MPU POWERQUICC 50MHZ 357PBGA

MPC855TCVR50D4

Manufacturer Part Number
MPC855TCVR50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC855TCVR50D4

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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15.2
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Freescale Semiconductor
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Platform/System PLL Ratio
LA[28:31] Signals
Binary Value of
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table
Table 46. CCB Clock Ratio
46.
16:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
12:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
Reserved
Reserved
Ratio Description
Clocking
67

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