MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 18

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

At recommended operating conditions with GV
DDR SDRAM
6.2
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
Table 13
6.2.2
Table 14
DDR SDRAM interface.
18
At recommended operating conditions with GV
AC input low voltage
AC input high voltage
MDQS—MDQ/MECC input skew per
byte
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS(n) output setup with respect to MCK
7) or ECC (MECC[{0...7}] if n = 8).
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the input AC timing specifications for the DDR SDRAM interface.
and
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
DDR SDRAM AC Electrical Characteristics
DDR SDRAM Input AC Timing Specifications
DDR SDRAM Output AC Timing Specifications
Parameter
Table 15
For DDR = 333 MHz
For DDR < 266 MHz
Parameter
provide the output AC timing specifications and measurement conditions for the
Table 13. DDR SDRAM Input AC Timing Specifications
DD
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
of 2.5 V ± 5%.
Symbol
t
DISKEW
V
V
IH
IL
Symbol
t
t
t
t
AOSKEW
DDKHAS
DDKHAX
DDKHCS
t
MCK
MV
1
REF
Min
—
—
+ 0.31
–1000
–1100
–1200
3.45
2.65
3.45
Min
2.8
4.6
2.0
3.8
2.8
4.6
6
MV
GV
REF
DD
1125
Max
750
– 0.31
+ 0.3
Max
200
300
400
10
—
—
—
Freescale Semiconductor
Unit
ps
V
V
Unit
ns
ps
ns
ns
ns
Notes
Notes
—
—
1
2
3
4
4
4